#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
+#include <linux/module.h>
#include <linux/string.h>
#include <asm/div64.h>
#include <asm/hardware.h>
u32 enable_mask;
};
+static struct clk clk_uart = {
+ .name = "UARTCLK",
+ .rate = 14745600,
+};
static struct clk clk_pll1 = {
.name = "pll1",
};
static struct clk *clocks[] = {
+ &clk_uart,
&clk_pll1,
&clk_f,
&clk_h,
return ERR_PTR(-ENOENT);
}
+EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return 0;
}
+EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
__raw_writel(value & ~clk->enable_mask, clk->enable_reg);
}
}
+EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
+EXPORT_SYMBOL(clk_get_rate);
void clk_put(struct clk *clk)
{
}
+EXPORT_SYMBOL(clk_put);
return (unsigned long)rate;
}
-void ep93xx_clock_init(void)
+static int __init ep93xx_clock_init(void)
{
u32 value;
printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
clk_f.rate / 1000000, clk_h.rate / 1000000,
clk_p.rate / 1000000);
+
+ return 0;
}
+arch_initcall(ep93xx_clock_init);