Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / clock.c

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 0de201c3d50b4a09d488109338d90a1df12597a9..e6e85b7b097b0e926f977034aea98515da2321fb 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -27,6 +27,7 @@
 
 #include <asm/arch/clock.h>
 #include <asm/arch/sram.h>
+#include <asm/div64.h>
 
 #include "prcm-regs.h"
 #include "memory.h"
@@ -442,7 +443,7 @@ static long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
 
 /*
  * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compenste for the shifted DLL value in unlock mode.
+ * This is needed to compensate for the shifted DLL value in unlock mode.
  */
 static u32 omap2_dll_force_needed(void)
 {
@@ -650,7 +651,7 @@ static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask,
                break;
        case CM_SYSCLKOUT_SEL1:
                div_addr = (u32)&PRCM_CLKOUT_CTRL;
-               if ((div_off == 3) || (div_off = 11))
+               if ((div_off == 3) || (div_off == 11))
                        mask= 0x3;
                break;
        case CM_CORE_SEL1:
@@ -1159,8 +1160,8 @@ int __init omap2_clk_init(void)
        clk_enable(&sync_32k_ick);
        clk_enable(&omapctrl_ick);
 
-       /* Force the APLLs active during bootup to avoid disabling and
-        * enabling them unnecessarily. */
+       /* Force the APLLs always active. The clocks are idled
+        * automatically by hardware. */
        clk_enable(&apll96_ck);
        clk_enable(&apll54_ck);
 
@@ -1173,12 +1174,3 @@ int __init omap2_clk_init(void)
 
        return 0;
 }
-
-static int __init omap2_disable_aplls(void)
-{
-       clk_disable(&apll96_ck);
-       clk_disable(&apll54_ck);
-
-       return 0;
-}
-late_initcall(omap2_disable_aplls);