break;
case CM_SYSCLKOUT_SEL1:
div_addr = (u32)&PRCM_CLKOUT_CTRL;
- if ((div_off == 3) || (div_off = 11))
+ if ((div_off == 3) || (div_off == 11))
mask= 0x3;
break;
case CM_CORE_SEL1:
clk_enable(&sync_32k_ick);
clk_enable(&omapctrl_ick);
- /* Force the APLLs active during bootup to avoid disabling and
- * enabling them unnecessarily. */
+ /* Force the APLLs always active. The clocks are idled
+ * automatically by hardware. */
clk_enable(&apll96_ck);
clk_enable(&apll54_ck);
return 0;
}
-
-static int __init omap2_disable_aplls(void)
-{
- clk_disable(&apll96_ck);
- clk_disable(&apll54_ck);
-
- return 0;
-}
-late_initcall(omap2_disable_aplls);