#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
+#include "prm.h"
+#include "cm.h"
+#include "prm_regbits_24xx.h"
+#include "cm_regbits_24xx.h"
+
static void omap2_sys_clk_recalc(struct clk * clk);
static void omap2_clksel_recalc(struct clk * clk);
static void omap2_followparent_recalc(struct clk * clk);
static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
static u32 omap2_clksel_get_divisor(struct clk *clk);
+/* REVISIT: should use a clock flag for this, not a magic number */
+#define PARENT_CONTROLS_CLOCK 0xff
#define RATE_IN_242X (1 << 0)
#define RATE_IN_243X (1 << 1)
+#define RATE_IN_343X (1 << 2)
/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
-#define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */
+#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
+/* 2420-PRCM I 660MHz core */
+#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
+#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
+#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
+#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
+ RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+ RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+ RI_CLKSEL_L4 | RI_CLKSEL_L3
+#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
+#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
+#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
+#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
+#define RI_SYNC_DSP (1 << 7) /* Activate sync */
+#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
+#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
+#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
+ RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
+ RI_CLKSEL_DSP
+#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
+#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
+
/* 2420-PRCM VII (boot) */
#define RVII_CLKSEL_L3 (1 << 0)
#define RVII_CLKSEL_L4 (1 << 5)
* boot (boot)
*/
+/* PRCM I target DPLL = 2*330MHz = 660MHz */
+#define MI_DPLL_MULT_12 (55 << 12)
+#define MI_DPLL_DIV_12 (1 << 8)
+#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
+ MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
+ MX_APLLS_CLIKIN_12
+
/*
* 2420 Equivalent - mode registers
* PRCM II , target DPLL = 2*300MHz = 600MHz
/*
* These represent optimal values for common parts, it won't work for all.
* As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the oppisite direction. If you
+ * become sub-optimal. The RFR value goes in the opposite direction. If you
* don't adjust it down as your clock period increases the refresh interval
* will not be met. Setting all parameters for complete worst case may work,
* but may cut memory performance by 2x. Due to errata the DLLs need to be
* By having the boot loader boot up in the fastest L4 speed available likely
* will result in something which you can switch between.
*/
+#define V24XX_SDRC_RFR_CTRL_165MHz (0x00044c00 | 1)
#define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
#define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
#define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
* Filling in table based on H4 boards and 2430-SDPs variants available.
* There are quite a few more rates combinations which could be defined.
*
- * When multiple values are defiend the start up will try and choose the
+ * When multiple values are defined the start up will try and choose the
* fastest one. If a 'fast' value is defined, then automatically, the /2
* one should be included as it can be used. Generally having more that
* one fast set does not make sense, as static timings need to be changed
* Note: This table needs to be sorted, fastest to slowest.
*-------------------------------------------------------------------------*/
static struct prcm_config rate_table[] = {
+ /* PRCM I - FAST */
+ {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
+ RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
+ RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
+ MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_165MHz,
+ RATE_IN_242X},
+
/* PRCM II - FAST */
{S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0x2,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
.recalc = &omap2_propagate_rate,
};
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0x6,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
.recalc = &omap2_propagate_rate,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 5,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = PARENT_CONTROLS_CLOCK,
.recalc = &omap2_propagate_rate,
};
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = PARENT_CONTROLS_CLOCK,
.recalc = &omap2_propagate_rate,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
.src_offset = 3,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = PARENT_CONTROLS_CLOCK,
.recalc = &omap2_propagate_rate,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
.recalc = &omap2_propagate_rate,
- .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
- .enable_bit = 0xff,
+ .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+ .enable_bit = PARENT_CONTROLS_CLOCK,
};
/* Secure timer, only available in secure mode */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 0,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
- .enable_bit = 7,
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
.rate_offset = 3,
.recalc = &omap2_clksel_recalc,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
.src_offset = 8,
- .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
- .enable_bit = 15,
+ .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
+ .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
.rate_offset = 11,
.recalc = &omap2_clksel_recalc,
};
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
- .enable_bit = 0,
+ .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
+ .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
.recalc = &omap2_propagate_rate,
};
DELAYED_APP | RATE_PROPAGATES |
CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
.recalc = &omap2_clksel_recalc,
};
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
.recalc = &omap2_clksel_recalc,
};
.parent = &dsp_fck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
- .rate_offset = 5,
- .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
- .enable_bit = 1, /* for ipi */
+ .rate_offset = 5,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
.recalc = &omap2_clksel_recalc,
};
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
- .rate_offset= 8,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 10,
+ .rate_offset = 8,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
.recalc = &omap2_clksel_recalc,
};
static struct clk iva1_mpu_int_ifck = {
.name = "iva1_mpu_int_ifck",
.parent = &iva1_ifck,
- .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
- .enable_bit = 8,
+ .flags = CLOCK_IN_OMAP242X,
+ .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
.recalc = &omap2_clksel_recalc,
};
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
CONFIG_PARTICIPANT,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 0,
- .rate_offset = 25,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
+ .rate_offset = 25,
.recalc = &omap2_clksel_recalc,
};
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
- .enable_bit = 1,
- .rate_offset = 20,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), /* bit 1 */
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
+ .rate_offset = 20,
.recalc = &omap2_clksel_recalc,
};
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
- .enable_bit = 2,
- .rate_offset= 0,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_3D_SHIFT,
+ .rate_offset = 0,
.recalc = &omap2_clksel_recalc,
};
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_GFX_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
- .enable_bit = 1,
- .rate_offset= 0,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_2D_SHIFT,
+ .rate_offset = 0,
.recalc = &omap2_clksel_recalc,
};
static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
.parent = &core_l3_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
- .enable_bit = 0,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), /* bit 0 */
+ .enable_bit = OMAP_EN_GFX_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
DELAYED_APP | CONFIG_PARTICIPANT,
.rate_offset = 0,
- .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
.recalc = &omap2_clksel_recalc,
};
.rate = 26000000,
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP243X | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
- .enable_bit = 1,
+ .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP2430_EN_OSC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.parent = &l4_ck,
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
- .enable_bit = 1,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), /* bit 1 */
+ .enable_bit = OMAP24XX_EN_SSI_SHIFT,
.recalc = &omap2_followparent_recalc,
};
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
.parent = &l4_ck, /* really both l3 and l4 */
- .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 0,
+ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &core_ck, /* Core or sys */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.rate_offset = 8,
.src_offset = 8,
.recalc = &omap2_clksel_recalc,
.name = "dss2_fck",
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
- RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 1,
+ RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED |
+ DELAYED_APP,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
.src_offset = 13,
.recalc = &omap2_followparent_recalc,
};
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_TV_SHIFT,
.recalc = &omap2_propagate_rate,
};
.name = "gpt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), /* Bit0 */
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_WKUP_SEL1,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN), /* Bit0 */
+ .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.src_offset = 0,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
- .enable_bit = 4,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit4 */
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 4,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.src_offset = 2,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
- .enable_bit = 5,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit5 */
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 5,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.src_offset = 4,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
- .enable_bit = 6,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit6 */
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 6,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.src_offset = 6,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
- .enable_bit = 7,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* Bit7 */
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 7,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.src_offset = 8,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt6_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 8,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit8 */
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 8,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
.src_offset = 10,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt7_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
- .enable_bit = 9,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit9 */
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 9,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.src_offset = 12,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt8_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
- .enable_bit = 10,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit10 */
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 10,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.src_offset = 14,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt9_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 11,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 11,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.src_offset = 16,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt10_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 12,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 12,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.src_offset = 18,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt11_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 13,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 13,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.src_offset = 20,
.recalc = &omap2_followparent_recalc,
};
.name = "gpt12_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
- .enable_bit = 14,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit14 */
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
CM_CORE_SEL2,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 14,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.src_offset = 22,
.recalc = &omap2_followparent_recalc,
};
+/* REVISIT: bit comment below wrong? */
static struct clk mcbsp1_ick = {
.name = "mcbsp1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), /* bit16 */
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 15,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_bit = 16,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp3_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 4,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp4_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 4,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 5,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mcbsp5_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 5,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 17,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 17,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 18,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 18,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 3,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 9,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 3,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 9,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "uart1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 21,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "uart1_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 21,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "uart2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 22,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "uart2_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 22,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "uart3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "uart3_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "gpios_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 2,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "gpios_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
- .enable_bit = 2,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 3,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
- .enable_bit = 3,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, OMAP24XX_CM_FCLKEN),
+ .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "sync_32k_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 1,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 4,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
static struct clk omapctrl_ick = {
.name = "omapctrl_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 5,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
.recalc = &omap2_followparent_recalc,
};
static struct clk icr_ick = {
.name = "icr_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
- .enable_bit = 6,
+ .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+ .enable_bit = OMAP2430_EN_ICR_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "cam_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 31,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "cam_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 31,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mailboxes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 30,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 29,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt4_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 29,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 28,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "wdt3_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 28,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mspro_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 27,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mspro_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 27,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 26,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmc_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 26,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "fac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 25,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "fac_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 25,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "eac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 24,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "eac_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 24,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "hdq_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 23,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "hdq_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 23,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 20,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 2,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 20,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
static struct clk i2chs2_fck = {
- .name = "i2chs2_fck",
+ .name = "i2chs_fck",
+ .id = 2,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 20,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 19,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.id = 1,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 19,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
static struct clk i2chs1_fck = {
- .name = "i2chs1_fck",
+ .name = "i2chs_fck",
+ .id = 1,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 19,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "vlynq_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
- .enable_bit = 3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "vlynq_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
- .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
- .enable_bit = 3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.src_offset = 15,
.recalc = &omap2_followparent_recalc,
};
.name = "sdrc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
- .enable_bit = 2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
+ .enable_bit = OMAP2430_EN_SDRC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "des_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_DES_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "sha_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 1,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_SHA_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "rng_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 2,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_RNG_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "aes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 3,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_AES_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "pka_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
- .enable_bit = 4,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
+ .enable_bit = OMAP24XX_EN_PKA_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "usb_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 0,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP24XX_EN_USB_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "usbhs_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 6,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_USBHS_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 7,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs1_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 7,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 8,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchs2_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 8,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "gpio5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 10,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "gpio5_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 10,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mdm_intc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
- .enable_bit = 11,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+ .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchsdb1_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 16,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
.recalc = &omap2_followparent_recalc,
};
.name = "mmchsdb2_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
- .enable_bit = 17,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
+ .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
.recalc = &omap2_followparent_recalc,
};