Merge omap-drivers

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / gpmc.c

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 54c836a984565daa81115a2d2ae2ab4a0b8ce3d4..7384cce3990894037d97b8707320809f8085d3d6 100644 (file)
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -22,7 +22,14 @@
 
 #undef DEBUG
 
+#ifdef CONFIG_ARCH_OMAP2420
 #define GPMC_BASE              0x6800a000
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+#define GPMC_BASE              0x6E000000
+#endif
+
 #define GPMC_REVISION          0x00
 #define GPMC_SYSCONFIG         0x10
 #define GPMC_SYSSTATUS         0x14
@@ -44,7 +51,6 @@
 #define GPMC_CS0               0x60
 #define GPMC_CS_SIZE           0x30
 
-#define GPMC_CS_NUM            8
 #define GPMC_MEM_START         0x00000000
 #define GPMC_MEM_END           0x3FFFFFFF
 #define BOOT_ROM_SPACE         0x100000        /* 1MB */
@@ -88,7 +94,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
-static unsigned long gpmc_get_fclk_period(void)
+unsigned long gpmc_get_fclk_period(void)
 {
        /* In picoseconds */
        return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
@@ -104,6 +110,13 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
        return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
+unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
+{
+       unsigned long ticks = gpmc_ns_to_ticks(time_ns);
+
+       return ticks * gpmc_get_fclk_period() / 1000;
+}
+
 #ifdef DEBUG
 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
                               int time, const char *name)
@@ -120,15 +133,21 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
        else
                ticks = gpmc_ns_to_ticks(time);
        nr_bits = end_bit - st_bit + 1;
-       if (ticks >= 1 << nr_bits)
+       if (ticks >= 1 << nr_bits) {
+#ifdef DEBUG
+               printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
+                               cs, name, time, ticks, 1 << nr_bits);
+#endif
                return -1;
+       }
 
        mask = (1 << nr_bits) - 1;
        l = gpmc_cs_read_reg(cs, reg);
 #ifdef DEBUG
-       printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
+       printk(KERN_INFO
+               "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
               cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
-              (l >> st_bit) & mask);
+                       (l >> st_bit) & mask, time);
 #endif
        l &= ~(mask << st_bit);
        l |= ticks << st_bit;
@@ -157,7 +176,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
        div = l / gpmc_get_fclk_period();
        if (div > 4)
                return -1;
-       if (div < 0)
+       if (div <= 0)
                div = 1;
 
        return div;
@@ -191,14 +210,19 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
        GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 
+       /* caller is expected to have initialized CONFIG1 to cover
+        * at least sync vs async
+        */
+       l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+       if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 #ifdef DEBUG
-       printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n",
-              cs, gpmc_get_fclk_period(), div);
+               printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
+                               cs, (div * gpmc_get_fclk_period()) / 1000, div);
 #endif
-
-       l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-       l &= ~0x03;
-       l |= (div - 1);
+               l &= ~0x03;
+               l |= (div - 1);
+               gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
+       }
 
        return 0;
 }