ARM:OMAP2: Add OVERO_GPIO_BT_XGATE to Overo board init

[linux-2.6-omap-h63xx.git] / arch / arm / mach-omap2 / pm24xx.c

diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 5d060de283a9c5d1d2f11f1262dca111e5039932..60ff04f3f4c08692af86ed7b8de399e08ac683a8 100644 (file)
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -35,15 +35,15 @@
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/irqs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sram.h>
-#include <asm/arch/control.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pm.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/board.h>
+#include <mach/irqs.h>
+#include <mach/clock.h>
+#include <mach/sram.h>
+#include <mach/control.h>
+#include <mach/gpio.h>
+#include <mach/pm.h>
+#include <mach/mux.h>
+#include <mach/dma.h>
+#include <mach/board.h>
 
 #include "prm.h"
 #include "prm-regbits-24xx.h"
@@ -52,15 +52,12 @@
 #include "sdrc.h"
 #include "pm.h"
 
-#include <asm/arch/powerdomain.h>
-#include <asm/arch/clockdomain.h>
-
-/* These addrs are in assembly language code to be patched at runtime */
-extern void *omap2_ocs_sdrc_power;
-extern void *omap2_ocs_sdrc_dlla_ctrl;
+#include <mach/powerdomain.h>
+#include <mach/clockdomain.h>
 
 static void (*omap2_sram_idle)(void);
-static void (*omap2_sram_suspend)(void __iomem *dllctrl);
+static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
+                                       void __iomem *sdrc_power);
 static void (*saved_idle)(void);
 
 static struct powerdomain *mpu_pwrdm;
@@ -125,7 +122,9 @@ static void omap2_enter_full_retention(void)
 
        serial_console_sleep(1);
        /* Jump to SRAM suspend code */
-       omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
+       omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
+                               OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
+                               OMAP_SDRC_REGADDR(SDRC_POWER));
 no_sleep:
        serial_console_sleep(0);
 
@@ -150,14 +149,16 @@ no_sleep:
        prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 
        /* MPU domain wake events */
-       l = __raw_readl(OMAP24XX_PRCM_IRQSTATUS_MPU);
+       l = prm_read_mod_reg(OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
        if (l & 0x01)
-               __raw_writel(0x01, OMAP24XX_PRCM_IRQSTATUS_MPU);
+               prm_write_mod_reg(0x01, OCP_MOD,
+                               OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
        if (l & 0x20)
-               __raw_writel(0x20, OMAP24XX_PRCM_IRQSTATUS_MPU);
+               prm_write_mod_reg(0x20, OCP_MOD,
+                               OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 
        /* Mask future PRCM-to-MPU interrupts */
-       __raw_writel(0x0, OMAP24XX_PRCM_IRQSTATUS_MPU);
+       prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRM_IRQSTATUS_MPU_OFFSET);
 }
 
 static int omap2_i2c_active(void)
@@ -350,7 +351,8 @@ static void __init prcm_setup_regs(void)
        struct powerdomain *pwrdm;
 
        /* Enable autoidle */
-       __raw_writel(OMAP24XX_AUTOIDLE, OMAP24XX_PRCM_SYSCONFIG);
+       prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
+                               OMAP24XX_PRM_SYSCONFIG_OFFSET);
 
        /* Set all domain wakeup dependencies */
        prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
@@ -456,16 +458,18 @@ static void __init prcm_setup_regs(void)
 
        /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
         * stabilisation */
-       __raw_writel(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_CLKSSETUP);
+       prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                       OMAP24XX_PRCM_CLKSSETUP_OFFSET);
 
        /* Configure automatic voltage transition */
-       __raw_writel(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_PRCM_VOLTSETUP);
-       __raw_writel(OMAP24XX_AUTO_EXTVOLT |
+       prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                       OMAP24XX_PRCM_VOLTSETUP_OFFSET);
+       prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
                      (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
                      OMAP24XX_MEMRETCTRL |
                      (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
                      (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
-                     OMAP24XX_PRCM_VOLTCTRL);
+                     OMAP24XX_GR_MOD, OMAP24XX_PRCM_VOLTCTRL_OFFSET);
 
        /* Enable wake-up events */
        prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
@@ -477,7 +481,7 @@ int __init omap2_pm_init(void)
        u32 l;
 
        printk(KERN_INFO "Power Management for OMAP2 initializing\n");
-       l = __raw_readl(OMAP24XX_PRCM_REVISION);
+       l = prm_read_mod_reg(OCP_MOD, OMAP24XX_PRM_REVISION_OFFSET);
        printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 
        /* Look up important powerdomains, clockdomains */
@@ -533,19 +537,13 @@ int __init omap2_pm_init(void)
         * These routines need to be in SRAM as that's the only
         * memory the MPU can see when it wakes up.
         */
-       omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
-                                        omap24xx_idle_loop_suspend_sz);
-
-       omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
-                                           omap24xx_cpu_suspend_sz);
-
-       /* Patch in the correct register addresses for multiboot */
-       omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_power,
-                          omap2_sram_suspend,
-                          OMAP_SDRC_REGADDR(SDRC_POWER));
-       omap_sram_patch_va(omap24xx_cpu_suspend, &omap2_ocs_sdrc_dlla_ctrl,
-                          omap2_sram_suspend,
-                          OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
+       if (cpu_is_omap24xx()) {
+               omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
+                                                omap24xx_idle_loop_suspend_sz);
+
+               omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
+                                                   omap24xx_cpu_suspend_sz);
+       }
 
        suspend_set_ops(&omap_pm_ops);
        pm_idle = omap2_pm_idle;