#include <asm/assembler.h>
#include <asm/arch/io.h>
#include <asm/hardware.h>
-
-#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
-
-#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP2_CM_BASE + 0x544)
-#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP2_PRM_BASE + 0x050)
-#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP2_PRM_BASE + 0x080)
-#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP2_CM_BASE + 0x500)
-#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP2_CM_BASE + 0x520)
-#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP2_CM_BASE + 0x540)
-
-#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP2_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP2_SDRC_BASE + 0x0a4)
+#include <linux/poison.h>
.text
mov r8, r3 @ capture force parameter
/* frequency shift down */
- ldr r2, cm_clksel2_pll @ get address of dpllout reg
+ ldr r2, omap2_sdi_cm_clksel2_pll @ get address of dpllout reg
mov r3, #0x1 @ value for 1x operation
str r3, [r2] @ go to L1-freq operation
bl voltage_shift @ go drop voltage
/* dll lock mode */
- ldr r11, sdrc_dlla_ctrl @ addr of dlla ctrl
+ ldr r11, omap2_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
ldr r10, [r11] @ get current val
cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
* wait for it to finish, use 32k sync counter, 1tick=31uS.
*/
voltage_shift:
- ldr r4, prcm_voltctrl @ get addr of volt ctrl.
+ ldr r4, omap2_sdi_prcm_voltctrl @ get addr of volt ctrl.
ldr r5, [r4] @ get value.
ldr r6, prcm_mask_val @ get value of mask
and r5, r5, r6 @ apply mask to clear bits
orr r5, r5, r3 @ build value for force
str r5, [r4] @ Force transition to L1
- ldr r3, timer_32ksynct_cr @ get addr of counter
+ ldr r3, omap2_sdi_timer_32ksynct_cr @ get addr of counter
ldr r5, [r3] @ get value
add r5, r5, #0x3 @ give it at most 93uS
volt_delay:
mov pc, lr @ back to caller.
/* relative load constants */
-cm_clksel2_pll:
- .word CM_CLKSEL2_PLL_V
-sdrc_dlla_ctrl:
- .word SDRC_DLLA_CTRL_V
-prcm_voltctrl:
- .word PRCM_VOLTCTRL_V
+ .globl omap2_sdi_cm_clksel2_pll
+ .globl omap2_sdi_sdrc_dlla_ctrl
+ .globl omap2_sdi_prcm_voltctrl
+ .globl omap2_sdi_timer_32ksynct_cr
+
+omap2_sdi_cm_clksel2_pll:
+ .word SRAM_VA_MAGIC
+omap2_sdi_sdrc_dlla_ctrl:
+ .word SRAM_VA_MAGIC
+omap2_sdi_prcm_voltctrl:
+ .word SRAM_VA_MAGIC
prcm_mask_val:
.word 0xFFFF3FFC
-timer_32ksynct_cr:
- .word TIMER_32KSYNCT_CR_V
+omap2_sdi_timer_32ksynct_cr:
+ .word SRAM_VA_MAGIC
ENTRY(sram_ddr_init_sz)
.word . - sram_ddr_init
mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
nop
nop
- ldr r6, ddr_sdrc_rfr_ctrl @ get addr of refresh reg
+ ldr r6, omap2_srs_sdrc_rfr_ctrl @ get addr of refresh reg
ldr r5, [r6] @ get value
mov r5, r5, lsr #8 @ isolate rfr field and drop burst
movne r5, r5, lsl #1 @ mult by 2 if to full
mov r5, r5, lsl #8 @ put rfr field back into place
add r5, r5, #0x1 @ turn on burst of 1
- ldr r4, ddr_cm_clksel2_pll @ get address of out reg
+ ldr r4, omap2_srs_cm_clksel2_pll @ get address of out reg
ldr r3, [r4] @ get curr value
orr r3, r3, #0x3
bic r3, r3, #0x3 @ clear lower bits
bne freq_out @ leave if SDR, no DLL function
/* With DDR, we need to take care of the DLL for the frequency change */
- ldr r2, ddr_sdrc_dlla_ctrl @ addr of dlla ctrl
+ ldr r2, omap2_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
str r1, [r2] @ write out new SDRC_DLLA_CTRL
add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
str r1, [r2] @ commit to SDRC_DLLB_CTRL
* wait for it to finish, use 32k sync counter, 1tick=31uS.
*/
voltage_shift_c:
- ldr r10, ddr_prcm_voltctrl @ get addr of volt ctrl
+ ldr r10, omap2_srs_prcm_voltctrl @ get addr of volt ctrl
ldr r8, [r10] @ get value
ldr r7, ddr_prcm_mask_val @ get value of mask
and r8, r8, r7 @ apply mask to clear bits
orr r8, r8, r7 @ build value for force
str r8, [r10] @ Force transition to L1
- ldr r10, ddr_timer_32ksynct @ get addr of counter
+ ldr r10, omap2_srs_timer_32ksynct @ get addr of counter
ldr r8, [r10] @ get value
add r8, r8, #0x2 @ give it at most 62uS (min 31+)
volt_delay_c:
bhi volt_delay_c @ not yet->branch
mov pc, lr @ back to caller
-ddr_cm_clksel2_pll:
- .word CM_CLKSEL2_PLL_V
-ddr_sdrc_dlla_ctrl:
- .word SDRC_DLLA_CTRL_V
-ddr_sdrc_rfr_ctrl:
- .word SDRC_RFR_CTRL_V
-ddr_prcm_voltctrl:
- .word PRCM_VOLTCTRL_V
+ .globl omap2_srs_cm_clksel2_pll
+ .globl omap2_srs_sdrc_dlla_ctrl
+ .globl omap2_srs_sdrc_rfr_ctrl
+ .globl omap2_srs_prcm_voltctrl
+ .globl omap2_srs_timer_32ksynct
+
+omap2_srs_cm_clksel2_pll:
+ .word SRAM_VA_MAGIC
+omap2_srs_sdrc_dlla_ctrl:
+ .word SRAM_VA_MAGIC
+omap2_srs_sdrc_rfr_ctrl:
+ .word SRAM_VA_MAGIC
+omap2_srs_prcm_voltctrl:
+ .word SRAM_VA_MAGIC
ddr_prcm_mask_val:
.word 0xFFFF3FFC
-ddr_timer_32ksynct:
- .word TIMER_32KSYNCT_CR_V
+omap2_srs_timer_32ksynct:
+ .word SRAM_VA_MAGIC
ENTRY(sram_reprogram_sdrc_sz)
.word . - sram_reprogram_sdrc
mcrr p15, 1, r8, r4, c12 @ preload into icache
pbegin:
/* move into fast relock bypass */
- ldr r8, pll_ctl @ get addr
+ ldr r8, omap2_ssp_pll_ctl @ get addr
ldr r5, [r8] @ get val
mvn r6, #0x3 @ clear mask
and r5, r5, r6 @ clear field
orr r7, r5, #0x2 @ fast relock val
str r7, [r8] @ go to fast relock
- ldr r4, pll_stat @ addr of stat
+ ldr r4, omap2_ssp_pll_stat @ addr of stat
block:
/* wait for bypass */
ldr r8, [r4] @ stat value
bne block @ loop if not
/* set new dpll dividers _after_ in bypass */
- ldr r4, pll_div @ get addr
+ ldr r4, omap2_ssp_pll_div @ get addr
str r0, [r4] @ set dpll ctrl val
- ldr r4, set_config @ get addr
+ ldr r4, omap2_ssp_set_config @ get addr
mov r8, #1 @ valid cfg msk
str r8, [r4] @ make dividers take
beq pend @ jump over dpll relock
/* relock DPLL with new vals */
- ldr r5, pll_stat @ get addr
- ldr r4, pll_ctl @ get addr
+ ldr r5, omap2_ssp_pll_stat @ get addr
+ ldr r4, omap2_ssp_pll_ctl @ get addr
orr r8, r7, #0x3 @ val for lock dpll
str r8, [r4] @ set val
mov r0, #1000 @ dead spin a bit
bne wait_lock @ wait if not
pend:
/* update memory timings & briefly lock dll */
- ldr r4, sdrc_rfr @ get addr
+ ldr r4, omap2_ssp_sdrc_rfr @ get addr
str r1, [r4] @ update refresh timing
- ldr r11, dlla_ctrl @ get addr of DLLA ctrl
+ ldr r11, omap2_ssp_dlla_ctrl @ get addr of DLLA ctrl
ldr r10, [r11] @ get current val
mvn r9, #0x4 @ mask to get clear bit2
and r10, r10, r9 @ clear bit2 for lock mode
nop
ldmfd sp!, {r0-r12, pc} @ restore regs and return
-set_config:
- .word PRCM_CLKCFG_CTRL_V
-pll_ctl:
- .word CM_CLKEN_PLL_V
-pll_stat:
- .word CM_IDLEST_CKGEN_V
-pll_div:
- .word CM_CLKSEL1_PLL_V
-sdrc_rfr:
- .word SDRC_RFR_CTRL_V
-dlla_ctrl:
- .word SDRC_DLLA_CTRL_V
+ .globl omap2_ssp_set_config
+ .globl omap2_ssp_pll_ctl
+ .globl omap2_ssp_pll_stat
+ .globl omap2_ssp_pll_div
+ .globl omap2_ssp_sdrc_rfr
+ .globl omap2_ssp_dlla_ctrl
+
+omap2_ssp_set_config:
+ .word SRAM_VA_MAGIC
+omap2_ssp_pll_ctl:
+ .word SRAM_VA_MAGIC
+omap2_ssp_pll_stat:
+ .word SRAM_VA_MAGIC
+omap2_ssp_pll_div:
+ .word SRAM_VA_MAGIC
+omap2_ssp_sdrc_rfr:
+ .word SRAM_VA_MAGIC
+omap2_ssp_dlla_ctrl:
+ .word SRAM_VA_MAGIC
ENTRY(sram_set_prcm_sz)
.word . - sram_set_prcm
projects / linux-2.6-omap-h63xx.git / blobdiff