]> pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - arch/arm/mm/Kconfig
[ARM] nommu: add ARM740T core support
[linux-2.6-omap-h63xx.git] / arch / arm / mm / Kconfig
index 9f860aa9c908c7a68bb4b37fd788468fc4fdf765..87f9fece960604635f1dd7f2a7837297bcf1af5b 100644 (file)
@@ -75,6 +75,21 @@ config CPU_ARM720T
          Say Y if you want support for the ARM720T processor.
          Otherwise, say N.
 
+# ARM740T
+config CPU_ARM740T
+       bool "Support ARM740T processor" if ARCH_INTEGRATOR
+       select CPU_32v4T
+       select CPU_ABRT_LV4T
+       select CPU_CACHE_V3     # although the core is v4t
+       select CPU_CP15_MPU
+       help
+         A 32-bit RISC processor with 8KB cache or 4KB variants,
+         write buffer and MPU(Protection Unit) built around
+         an ARM7TDMI core.
+
+         Say Y if you want support for the ARM740T processor.
+         Otherwise, say N.
+
 # ARM920T
 config CPU_ARM920T
        bool "Support ARM920T processor"
@@ -436,7 +451,7 @@ comment "Processor Features"
 
 config ARM_THUMB
        bool "Support Thumb user binaries"
-       depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
+       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -473,7 +488,7 @@ config CPU_DCACHE_DISABLE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you