Merge branch 's3c-move' into devel

[linux-2.6-omap-h63xx.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3a6c8ec34cd96b29f3b585331ecf4a8cdf8dd3eb..d1193884d76d9ce4540b5d2a9d11e94e0233536b 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -187,7 +187,7 @@ config CPU_ARM926T
                ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
                ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
                ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
-               ARCH_NS9XXX || ARCH_DAVINCI
+               ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
        default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
                ARCH_OMAP730 || ARCH_OMAP16XX || \
                ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
@@ -428,7 +428,7 @@ config CPU_32v6K
 # ARMv7
 config CPU_V7
        bool "Support ARM V7 processor"
-       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
+       depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3
        select CPU_32v6K
        select CPU_32v7
        select CPU_ABRT_EV7
@@ -735,6 +735,14 @@ config CACHE_FEROCEON_L2
        help
          This option enables the Feroceon L2 cache controller.
 
+config CACHE_FEROCEON_L2_WRITETHROUGH
+       bool "Force Feroceon L2 cache write through"
+       depends on CACHE_FEROCEON_L2
+       default n
+       help
+         Say Y here to use the Feroceon L2 cache in writethrough mode.
+         Unless you specifically require this, say N for writeback mode.
+
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
@@ -742,3 +750,11 @@ config CACHE_L2X0
        select OUTER_CACHE
        help
          This option enables the L2x0 PrimeCell.
+
+config CACHE_XSC3L2
+       bool "Enable the L2 cache on XScale3"
+       depends on CPU_XSC3
+       default y
+       select OUTER_CACHE
+       help
+         This option enables the L2 cache on XScale3.