Merge by hand (conflicts in sr.c)

[linux-2.6-omap-h63xx.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 48bac7da8c70589dba5f06be40b325457398c640..db5e47dfc303dce4a49b9ca54db0ab1f0e3673af 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -62,7 +62,7 @@ config CPU_ARM720T
 # ARM920T
 config CPU_ARM920T
        bool "Support ARM920T processor" if !ARCH_S3C2410
-       depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX
+       depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000
        default y if ARCH_S3C2410
        select CPU_32v4
        select CPU_ABRT_EV4T
@@ -101,7 +101,7 @@ config CPU_ARM922T
 
 # ARM925T
 config CPU_ARM925T
-       bool "Support ARM925T processor" if ARCH_OMAP
+       bool "Support ARM925T processor" if ARCH_OMAP1
        depends on ARCH_OMAP1510
        default y if ARCH_OMAP1510
        select CPU_32v4
@@ -228,7 +228,6 @@ config CPU_SA1100
        select CPU_CACHE_V4WB
        select CPU_CACHE_VIVT
        select CPU_TLB_V4WB
-       select CPU_MINICACHE
 
 # XScale
 config CPU_XSCALE
@@ -239,7 +238,6 @@ config CPU_XSCALE
        select CPU_ABRT_EV5T
        select CPU_CACHE_VIVT
        select CPU_TLB_V4WBI
-       select CPU_MINICACHE
 
 # ARMv6
 config CPU_V6
@@ -345,11 +343,6 @@ config CPU_TLB_V4WBI
 config CPU_TLB_V6
        bool
 
-config CPU_MINICACHE
-       bool
-       help
-         Processor has a minicache.
-
 comment "Processor Features"
 
 config ARM_THUMB
@@ -391,7 +384,7 @@ config CPU_DCACHE_DISABLE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DISABLE_DCACHE
+       depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
@@ -429,3 +422,11 @@ config HAS_TLS_REG
          assume directly accessing that register and always obtain the
          expected value only on ARMv7 and above.
 
+config NEEDS_SYSCALL_FOR_CMPXCHG
+       bool
+       default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
+       help
+         SMP on a pre-ARMv6 processor?  Well OK then.
+         Forget about fast user space cmpxchg support.
+         It is just not possible.
+