Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-mmc

[linux-2.6-omap-h63xx.git] / arch / arm / mm / flush.c

diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 191788fb18d13a4f3adad73afd92a649c0c7ff21..d438ce41cdd5c5ef76d8b1b6d9507a35bbfb6205 100644 (file)
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -16,6 +16,7 @@
 #include <asm/tlbflush.h>
 
 #ifdef CONFIG_CPU_CACHE_VIPT
+
 #define ALIAS_FLUSH_START      0xffff4000
 
 #define TOP_PTE(x)     pte_offset_kernel(top_pmd, x)
@@ -23,16 +24,95 @@
 static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
 {
        unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
+       const int zero = 0;
 
        set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL));
        flush_tlb_kernel_page(to);
 
        asm(    "mcrr   p15, 0, %1, %0, c14\n"
-       "       mcrr    p15, 0, %1, %0, c5\n"
+       "       mcr     p15, 0, %2, c7, c10, 4\n"
+       "       mcr     p15, 0, %2, c7, c5, 0\n"
            :
-           : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES)
+           : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
            : "cc");
 }
+
+void flush_cache_mm(struct mm_struct *mm)
+{
+       if (cache_is_vivt()) {
+               if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
+                       __cpuc_flush_user_all();
+               return;
+       }
+
+       if (cache_is_vipt_aliasing()) {
+               asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
+               "       mcr     p15, 0, %0, c7, c5, 0\n"
+               "       mcr     p15, 0, %0, c7, c10, 4"
+                   :
+                   : "r" (0)
+                   : "cc");
+       }
+}
+
+void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
+{
+       if (cache_is_vivt()) {
+               if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
+                       __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
+                                               vma->vm_flags);
+               return;
+       }
+
+       if (cache_is_vipt_aliasing()) {
+               asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
+               "       mcr     p15, 0, %0, c7, c5, 0\n"
+               "       mcr     p15, 0, %0, c7, c10, 4"
+                   :
+                   : "r" (0)
+                   : "cc");
+       }
+}
+
+void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
+{
+       if (cache_is_vivt()) {
+               if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
+                       unsigned long addr = user_addr & PAGE_MASK;
+                       __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
+               }
+               return;
+       }
+
+       if (cache_is_vipt_aliasing())
+               flush_pfn_alias(pfn, user_addr);
+}
+
+void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
+                        unsigned long uaddr, void *kaddr,
+                        unsigned long len, int write)
+{
+       if (cache_is_vivt()) {
+               if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
+                       unsigned long addr = (unsigned long)kaddr;
+                       __cpuc_coherent_kern_range(addr, addr + len);
+               }
+               return;
+       }
+
+       if (cache_is_vipt_aliasing()) {
+               flush_pfn_alias(page_to_pfn(page), uaddr);
+               return;
+       }
+
+       /* VIPT non-aliasing cache */
+       if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask) &&
+           vma->vm_flags | VM_EXEC) {
+               unsigned long addr = (unsigned long)kaddr;
+               /* only flushing the kernel mapping on non-aliasing VIPT */
+               __cpuc_coherent_kern_range(addr, addr + len);
+       }
+}
 #else
 #define flush_pfn_alias(pfn,vaddr)     do { } while (0)
 #endif
@@ -103,14 +183,19 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
  *  space mappings, we can be lazy and remember that we may have dirty
  *  kernel cache lines for later.  Otherwise, we assume we have
  *  aliasing mappings.
+ *
+ * Note that we disable the lazy flush for SMP.
  */
 void flush_dcache_page(struct page *page)
 {
        struct address_space *mapping = page_mapping(page);
 
+#ifndef CONFIG_SMP
        if (mapping && !mapping_mapped(mapping))
                set_bit(PG_dcache_dirty, &page->flags);
-       else {
+       else
+#endif
+       {
                __flush_dcache_page(mapping, page);
                if (mapping && cache_is_vivt())
                        __flush_dcache_aliases(mapping, page);