]> pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - arch/arm/mm/mm-armv.c
Pull pnpacpi into release branch
[linux-2.6-omap-h63xx.git] / arch / arm / mm / mm-armv.c
index 5e5d05bcad50012acee900405497cc3e2707916d..95273de4f772515780e2eac97ed2ae892ac52a0d 100644 (file)
@@ -376,7 +376,7 @@ void __init build_mem_type_table(void)
                ecc_mask = 0;
        }
 
-       if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
+       if (cpu_arch <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) {
                for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
                        if (mem_types[i].prot_l1)
                                mem_types[i].prot_l1 |= PMD_BIT4;
@@ -388,6 +388,17 @@ void __init build_mem_type_table(void)
        cp = &cache_policies[cachepolicy];
        kern_pgprot = user_pgprot = cp->pte;
 
+       /*
+        * Enable CPU-specific coherency if supported.
+        * (Only available on XSC3 at the moment.)
+        */
+       if (arch_is_coherent()) {
+               if (cpu_is_xsc3()) {
+                       mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
+                       mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT;
+               }
+       }
+
        /*
         * ARMv6 and above have extended page tables.
         */
@@ -620,7 +631,7 @@ void setup_mm_for_reboot(char mode)
                pgd = init_mm.pgd;
 
        base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
-       if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ)
+       if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
                base_pmdval |= PMD_BIT4;
 
        for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {