#include <asm/hardware.h>
#include <asm/mach/pci.h>
#include <asm/hardware/iop3xx.h>
+#include <asm/mach-types.h>
// #define DEBUG
*IOP3XX_IATVR2 = PHYS_OFFSET;
/* Outbound window 0 */
- *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
+ *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
*IOP3XX_OUMWTVR0 = 0;
/* Outbound window 1 */
- *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
+ *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE;
*IOP3XX_OUMWTVR1 = 0;
/* BAR 3 ( Disabled ) */
/* Setup the I/O Bar
*/
- *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
+ *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
/* Enable inbound and outbound cycles
*/
/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
int init_atu;
-void __init iop3xx_pci_preinit(void)
-{
- if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
- iop3xx_atu_disable();
- iop3xx_atu_setup();
- }
+int iop3xx_get_init_atu(void) {
+ /* check if default has been overridden */
+ if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
+ return init_atu;
+ else
+ return IOP3XX_INIT_ATU_DISABLE;
+}
+static void __init iop3xx_atu_debug(void)
+{
DBG("PCI: Intel IOP3xx PCI init.\n");
DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
*IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
}
+/* for platforms that might be host-bus-adapters */
+void __init iop3xx_pci_preinit_cond(void)
+{
+ if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
+ iop3xx_atu_disable();
+ iop3xx_atu_setup();
+ iop3xx_atu_debug();
+ }
+}
+
+void __init iop3xx_pci_preinit(void)
+{
+ iop3xx_atu_disable();
+ iop3xx_atu_setup();
+ iop3xx_atu_debug();
+}
+
/* allow init_atu to be user overridden */
static int __init iop3xx_init_atu_setup(char *str)
{