[SCSI] sd: Fix handling of NO_SENSE check condition

[linux-2.6-omap-h63xx.git] / arch / blackfin / kernel / reboot.c

diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index ae28aac6fec156c01bfd3095a8002de8b9dc9863..ae97ca407b0dfe0a2e17809e0d2d542c65376677 100644 (file)
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -10,35 +10,58 @@
 #include <asm/bfin-global.h>
 #include <asm/reboot.h>
 #include <asm/system.h>
+#include <asm/bfrom.h>
 
-#if defined(BF537_FAMILY) || defined(BF533_FAMILY) || defined(BF527_FAMILY)
-#define SYSCR_VAL      0x0
-#elif defined(BF561_FAMILY)
-#define SYSCR_VAL      0x20
-#elif defined(BF548_FAMILY)
-#define SYSCR_VAL      0x10
-#endif
-
-/* A system soft reset makes external memory unusable
- * so force this function into L1.
+/* A system soft reset makes external memory unusable so force
+ * this function into L1.  We use the compiler ssync here rather
+ * than SSYNC() because it's safe (no interrupts and such) and
+ * we save some L1.  We do not need to force sanity in the SYSCR
+ * register as the BMODE selection bit is cleared by the soft
+ * reset while the Core B bit (on dual core parts) is cleared by
+ * the core reset.
  */
 __attribute__((l1_text))
-void bfin_reset(void)
+static void bfin_reset(void)
 {
-       /* force BMODE and disable Core B (as needed) */
-       bfin_write_SYSCR(SYSCR_VAL);
-
-       /* we use asm ssync here because it's save and we save some L1 */
-       asm("ssync;");
+       /* Wait for completion of "system" events such as cache line
+        * line fills so that we avoid infinite stalls later on as
+        * much as possible.  This code is in L1, so it won't trigger
+        * any such event after this point in time.
+        */
+       __builtin_bfin_ssync();
 
        while (1) {
-               /* initiate system soft reset with magic 0x7 */
+               /* Initiate System software reset. */
                bfin_write_SWRST(0x7);
-               asm("ssync;");
-               /* clear system soft reset */
+
+               /* Due to the way reset is handled in the hardware, we need
+                * to delay for 10 SCLKS.  The only reliable way to do this is
+                * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
+                * we'll assume worse case which is a 1:15 ratio.
+                */
+               asm(
+                       "LSETUP (1f, 1f) LC0 = %0\n"
+                       "1: nop;"
+                       :
+                       : "a" (15 * 10)
+                       : "LC0", "LB0", "LT0"
+               );
+
+               /* Clear System software reset */
                bfin_write_SWRST(0);
-               asm("ssync;");
-               /* issue core reset */
+
+               /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
+                * though as the System state is all reset now.
+                */
+               asm(
+                       "LSETUP (1f, 1f) LC1 = %0\n"
+                       "1: nop;"
+                       :
+                       : "a" (15 * 1)
+                       : "LC1", "LB1", "LT1"
+               );
+
+               /* Issue core reset */
                asm("raise 1");
        }
 }
@@ -52,7 +75,14 @@ void machine_restart(char *cmd)
 {
        native_machine_restart(cmd);
        local_irq_disable();
-       bfin_reset();
+       if (ANOMALY_05000353 || ANOMALY_05000386)
+               bfin_reset();
+       else
+               /* the bootrom checks to see how it was reset and will
+                * automatically perform a software reset for us when
+                * it starts executing boot
+                */
+               asm("raise 1;");
 }
 
 __attribute__((weak))