#include <asm/trace.h>
#if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach-common/clocks.h>
#include <asm/mach/mem_init.h>
#endif
-.global __rambase
-.global __ramstart
-.global __ramend
.extern ___bss_stop
.extern ___bss_start
.extern _bf53x_relocate_l1_mem
ENTRY(__start)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
- /* Set the SYSCFG register:
- * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
- */
- R0 = 0x36;
+ /* Enable Cycle Counter and Nesting Of Interrupts */
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
+ R0 = SYSCFG_SNEN;
+#else
+ R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
SYSCFG = R0;
R0 = 0;
M2 = r0;
M3 = r0;
- trace_buffer_start(p0,r0);
+ trace_buffer_init(p0,r0);
P0 = R1;
R0 = R1;
/* Turn off the icache */
- p0.l = (IMEM_CONTROL & 0xFFFF);
- p0.h = (IMEM_CONTROL >> 16);
+ p0.l = LO(IMEM_CONTROL);
+ p0.h = HI(IMEM_CONTROL);
R1 = [p0];
R0 = ~ENICPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
STI R2;
#endif
/* Turn off the dcache */
- p0.l = (DMEM_CONTROL & 0xFFFF);
- p0.h = (DMEM_CONTROL >> 16);
+ p0.l = LO(DMEM_CONTROL);
+ p0.h = HI(DMEM_CONTROL);
R1 = [p0];
R0 = ~ENDCPLB;
R0 = R0 & R1;
/* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
CLI R2;
SSYNC;
#endif
[p0] = R0;
SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
STI R2;
#endif
*/
p0.h = hi(BFIN_PORT_MUX);
p0.l = lo(BFIN_PORT_MUX);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
R0.L = W[P0]; /* Read */
SSYNC;
#endif
R0 = (PGDE_UART | PFTE_UART)(Z);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
W[P0] = R0.L; /* Write */
SSYNC;
#endif
p0.h = hi(PORTF_FER);
p0.l = lo(PORTF_FER);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
R0.L = W[P0]; /* Read */
SSYNC;
#endif
R0 = 0x000F(Z);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
W[P0] = R0.L; /* Write */
SSYNC;
#endif
SSYNC;
#endif
-#ifdef CONFIG_BF537_PORT_H
- p0.h = hi(PORTH_FER);
- p0.l = lo(PORTH_FER);
- R0.L = W[P0]; /* Read */
- SSYNC;
- R0 = 0x0000;
- W[P0] = R0.L; /* Write */
- SSYNC;
- W[P0] = R0.L; /* Disable peripheral function of PORTH */
- SSYNC;
-#endif
-
/* Initialise UART - when booting from u-boot, the UART is not disabled
* so if we dont initalize here, our serial console gets hosed */
- p0.h = hi(UART_LCR);
- p0.l = lo(UART_LCR);
+ p0.h = hi(BFIN_UART_LCR);
+ p0.l = lo(BFIN_UART_LCR);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable DLL writes */
ssync;
- p0.h = hi(UART_DLL);
- p0.l = lo(UART_DLL);
+ p0.h = hi(BFIN_UART_DLL);
+ p0.l = lo(BFIN_UART_DLL);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_DLH);
- p0.l = lo(UART_DLH);
+ p0.h = hi(BFIN_UART_DLH);
+ p0.l = lo(BFIN_UART_DLH);
r0 = 0x00(Z);
w[p0] = r0.L;
ssync;
- p0.h = hi(UART_GCTL);
- p0.l = lo(UART_GCTL);
+ p0.h = hi(BFIN_UART_GCTL);
+ p0.l = lo(BFIN_UART_GCTL);
r0 = 0x0(Z);
w[p0] = r0.L; /* To enable UART clock */
ssync;
fp = sp;
usp = sp;
+#ifdef CONFIG_EARLY_PRINTK
+ SP += -12;
+ call _init_early_exception_vectors;
+ SP += 12;
+#endif
+
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
#if CONFIG_BFIN_KERNEL_CLOCK
p0.l = .LWAIT_HERE;
p0.h = .LWAIT_HERE;
reti = p0;
-#if defined(ANOMALY_05000281)
+#if ANOMALY_05000281
nop; nop; nop;
#endif
rti;
w[p0] = r0.l;
ssync;
- p0.l = (EBIU_SDBCTL & 0xFFFF);
- p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
+ p0.l = LO(EBIU_SDBCTL);
+ p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-ENTRY(_bfin_reset)
- /* No more interrupts to be handled*/
- CLI R6;
- SSYNC;
-
-#if defined(CONFIG_MTD_M25P80)
- /*
- * The following code fix the SPI flash reboot issue,
- * /CS signal of the chip which is using PF10 return to GPIO mode
- */
- p0.h = hi(PORTF_FER);
- p0.l = lo(PORTF_FER);
- r0.l = 0x0000;
- w[p0] = r0.l;
- SSYNC;
-
- /* /CS return to high */
- p0.h = hi(PORTFIO);
- p0.l = lo(PORTFIO);
- r0.l = 0xFFFF;
- w[p0] = r0.l;
- SSYNC;
-
- /* Delay some time, This is necessary */
- r1.h = 0;
- r1.l = 0x400;
- p1 = r1;
- lsetup (.L_delay_lab1, .L_delay_lab1_end) lc1 = p1;
-.L_delay_lab1:
- r0.h = 0;
- r0.l = 0x8000;
- p0 = r0;
- lsetup (.L_delay_lab0, .L_delay_lab0_end) lc0 = p0;
-.L_delay_lab0:
- nop;
-.L_delay_lab0_end:
- nop;
-.L_delay_lab1_end:
- nop;
-#endif
-
- /* Clear the IMASK register */
- p0.h = hi(IMASK);
- p0.l = lo(IMASK);
- r0 = 0x0;
- [p0] = r0;
-
- /* Clear the ILAT register */
- p0.h = hi(ILAT);
- p0.l = lo(ILAT);
- r0 = [p0];
- [p0] = r0;
- SSYNC;
-
- /* make sure SYSCR is set to use BMODE */
- P0.h = hi(SYSCR);
- P0.l = lo(SYSCR);
- R0.l = 0x0;
- W[P0] = R0.l;
- SSYNC;
-
- /* issue a system soft reset */
- P1.h = hi(SWRST);
- P1.l = lo(SWRST);
- R1.l = 0x0007;
- W[P1] = R1;
- SSYNC;
-
- /* clear system soft reset */
- R0.l = 0x0000;
- W[P0] = R0;
- SSYNC;
-
- /* issue core reset */
- raise 1;
-
- RTS;
-ENDPROC(_bfin_reset)
-
-.data
-
-/*
- * Set up the usable of RAM stuff. Size of RAM is determined then
- * an initial stack set up at the end.
- */
-
-.align 4
-__rambase:
-.long 0
-__ramstart:
-.long 0
-__ramend:
-.long 0
projects / linux-2.6-omap-h63xx.git / blobdiff