.Lno_dcache_b:
R7 = [SP++];
RTS;
+ENDPROC(_cache_invalidate)
/* Invalidate the Entire Instruction cache by
* disabling IMC bit
( R7:5) = [SP++];
RTS;
+ENDPROC(_invalidate_entire_icache)
+ENDPROC(_icache_invalidate)
/*
* blackfin_cache_flush_range(start, end)
IFLUSH [P0];
SSYNC;
RTS;
+ENDPROC(_blackfin_icache_flush_range)
/*
* blackfin_icache_dcache_flush_range(start, end)
FLUSH [P0];
SSYNC;
RTS;
+ENDPROC(_blackfin_icache_dcache_flush_range)
/* Throw away all D-cached data in specified region without any obligation to
* write them back. However, we must clean the D-cached entries around the
FLUSHINV[P0];
SSYNC;
RTS;
+ENDPROC(_blackfin_dcache_invalidate_range)
/* Invalidate the Entire Data cache by
* clearing DMC[1:0] bits
( R7:6) = [SP++];
RTS;
+ENDPROC(_dcache_invalidate)
+ENDPROC(_invalidate_entire_dcache)
ENTRY(_blackfin_dcache_flush_range)
R2 = -L1_CACHE_BYTES;
FLUSH[P0];
SSYNC;
RTS;
+ENDPROC(_blackfin_dcache_flush_range)
ENTRY(_blackfin_dflush_page)
P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
.Lfl1: FLUSH [P0++];
SSYNC;
RTS;
+ENDPROC(_blackfin_dflush_page)