[PATCH] i386: inline assembler: cleanup and encapsulate descriptor and task register...

[linux-2.6-omap-h63xx.git] / arch / i386 / power / cpu.c

diff --git a/arch/i386/power/cpu.c b/arch/i386/power/cpu.c
index 6f521cf19a133924b026b13bb3695218fd2a2e6b..c7a6436aa938039ec9d4bcbb6b7c49d5bc2ebdcd 100644 (file)
--- a/arch/i386/power/cpu.c
+++ b/arch/i386/power/cpu.c
@@ -22,9 +22,11 @@
 #include <linux/device.h>
 #include <linux/suspend.h>
 #include <linux/acpi.h>
+
 #include <asm/uaccess.h>
 #include <asm/acpi.h>
 #include <asm/tlbflush.h>
+#include <asm/processor.h>
 
 static struct saved_context saved_context;
 
@@ -33,8 +35,6 @@ unsigned long saved_context_esp, saved_context_ebp;
 unsigned long saved_context_esi, saved_context_edi;
 unsigned long saved_context_eflags;
 
-extern void enable_sep_cpu(void *);
-
 void __save_processor_state(struct saved_context *ctxt)
 {
        kernel_fpu_begin();
@@ -42,26 +42,25 @@ void __save_processor_state(struct saved_context *ctxt)
        /*
         * descriptor tables
         */
-       asm volatile ("sgdt %0" : "=m" (ctxt->gdt_limit));
-       asm volatile ("sidt %0" : "=m" (ctxt->idt_limit));
-       asm volatile ("sldt %0" : "=m" (ctxt->ldt));
-       asm volatile ("str %0"  : "=m" (ctxt->tr));
+       store_gdt(&ctxt->gdt_limit);
+       store_idt(&ctxt->idt_limit);
+       store_tr(ctxt->tr);
 
        /*
         * segment registers
         */
-       asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
-       asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
-       asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
-       asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
+       savesegment(es, ctxt->es);
+       savesegment(fs, ctxt->fs);
+       savesegment(gs, ctxt->gs);
+       savesegment(ss, ctxt->ss);
 
        /*
         * control registers 
         */
-       asm volatile ("movl %%cr0, %0" : "=r" (ctxt->cr0));
-       asm volatile ("movl %%cr2, %0" : "=r" (ctxt->cr2));
-       asm volatile ("movl %%cr3, %0" : "=r" (ctxt->cr3));
-       asm volatile ("movl %%cr4, %0" : "=r" (ctxt->cr4));
+       ctxt->cr0 = read_cr0();
+       ctxt->cr2 = read_cr2();
+       ctxt->cr3 = read_cr3();
+       ctxt->cr4 = read_cr4();
 }
 
 void save_processor_state(void)
@@ -107,39 +106,38 @@ static void fix_processor_context(void)
 
 void __restore_processor_state(struct saved_context *ctxt)
 {
-
        /*
         * control registers
         */
-       asm volatile ("movl %0, %%cr4" :: "r" (ctxt->cr4));
-       asm volatile ("movl %0, %%cr3" :: "r" (ctxt->cr3));
-       asm volatile ("movl %0, %%cr2" :: "r" (ctxt->cr2));
-       asm volatile ("movl %0, %%cr0" :: "r" (ctxt->cr0));
+       write_cr4(ctxt->cr4);
+       write_cr3(ctxt->cr3);
+       write_cr2(ctxt->cr2);
+       write_cr2(ctxt->cr0);
 
        /*
-        * segment registers
+        * now restore the descriptor tables to their proper values
+        * ltr is done i fix_processor_context().
         */
-       asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
-       asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
-       asm volatile ("movw %0, %%gs" :: "r" (ctxt->gs));
-       asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
+       load_gdt(&ctxt->gdt_limit);
+       load_idt(&ctxt->idt_limit);
 
        /*
-        * now restore the descriptor tables to their proper values
-        * ltr is done i fix_processor_context().
+        * segment registers
         */
-       asm volatile ("lgdt %0" :: "m" (ctxt->gdt_limit));
-       asm volatile ("lidt %0" :: "m" (ctxt->idt_limit));
-       asm volatile ("lldt %0" :: "m" (ctxt->ldt));
+       loadsegment(es, ctxt->es);
+       loadsegment(fs, ctxt->fs);
+       loadsegment(gs, ctxt->gs);
+       loadsegment(ss, ctxt->ss);
 
        /*
         * sysenter MSRs
         */
        if (boot_cpu_has(X86_FEATURE_SEP))
-               enable_sep_cpu(NULL);
+               enable_sep_cpu();
 
        fix_processor_context();
        do_fpu_end();
+       mtrr_ap_init();
 }
 
 void restore_processor_state(void)