[MIPS] Kill redundant EXTRA_AFLAGS

[linux-2.6-omap-h63xx.git] / arch / mips / cobalt / setup.c

diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index c01a0170e5903e51851d9743566ea3645988bf7f..415ff8710b553d3e76ea3f0589d70da63cedbb67 100644 (file)
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -23,7 +23,6 @@
 #include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/gt64120.h>
-#include <asm/serial.h>
 
 #include <asm/mach-cobalt/cobalt.h>
 
@@ -51,24 +50,24 @@ const char *get_system_type(void)
 
 void __init plat_timer_setup(struct irqaction *irq)
 {
-       /* Load timer value for 1KHz (TCLK is 50MHz) */
-       GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
+       /* Load timer value for HZ (TCLK is 50MHz) */
+       GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
 
        /* Enable timer */
-       GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
+       GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
 
        /* Register interrupt */
        setup_irq(COBALT_GALILEO_IRQ, irq);
 
        /* Enable interrupt */
-       GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
+       GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
 }
 
 extern struct pci_ops gt64111_pci_ops;
 
 static struct resource cobalt_mem_resource = {
-       .start  = GT64111_MEM_BASE,
-       .end    = GT64111_MEM_END,
+       .start  = GT_DEF_PCI0_MEM0_BASE,
+       .end    = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
        .name   = "PCI memory",
        .flags  = IORESOURCE_MEM
 };
@@ -116,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = {
        .mem_resource   = &cobalt_mem_resource,
        .mem_offset     = 0,
        .io_resource    = &cobalt_io_resource,
-       .io_offset      = 0 - GT64111_IO_BASE
+       .io_offset      = 0 - GT_DEF_PCI0_IO_BASE,
 };
 
 void __init plat_mem_setup(void)
@@ -129,9 +128,9 @@ void __init plat_mem_setup(void)
        _machine_halt = cobalt_machine_halt;
        pm_power_off = cobalt_machine_power_off;
 
-        set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
+       set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
 
-       /* I/O port resource must include UART and LCD/buttons */
+       /* I/O port resource must include LCD/buttons */
        ioport_resource.end = 0x0fffffff;
 
        /* request I/O space for devices used on all i[345]86 PCs */
@@ -140,7 +139,7 @@ void __init plat_mem_setup(void)
 
         /* Read the cobalt id register out of the PCI config space */
         PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
-        cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
+        cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
         cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
         cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
 
@@ -150,24 +149,24 @@ void __init plat_mem_setup(void)
        register_pci_controller(&cobalt_pci_controller);
 #endif
 
-#ifdef CONFIG_SERIAL_8250
        if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
-
 #ifdef CONFIG_EARLY_PRINTK
                cobalt_early_console();
 #endif
 
+#ifdef CONFIG_SERIAL_8250
                uart.line       = 0;
                uart.type       = PORT_UNKNOWN;
                uart.uartclk    = 18432000;
                uart.irq        = COBALT_SERIAL_IRQ;
-               uart.flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-               uart.iobase     = 0xc800000;
-               uart.iotype     = UPIO_PORT;
+               uart.flags      = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
+                                 UPF_SKIP_TEST;
+               uart.iotype     = UPIO_MEM;
+               uart.mapbase    = 0x1c800000;
 
                early_serial_setup(&uart);
-       }
 #endif
+       }
 }
 
 /*
@@ -205,8 +204,7 @@ void __init prom_init(void)
        add_memory_region(0x0, memsz, BOOT_MEM_RAM);
 }
 
-unsigned long __init prom_free_prom_memory(void)
+void __init prom_free_prom_memory(void)
 {
        /* Nothing to do! */
-       return 0;
 }