Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-omap-h63xx.git] / arch / mips / include / asm / atomic.h

diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 1232be3885b01caa879576f3a9a1fd6dc91c8dbc..1b332e15ab528522c19e4769c7691435e843dce1 100644 (file)
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -15,13 +15,12 @@
 #define _ASM_ATOMIC_H
 
 #include <linux/irqflags.h>
+#include <linux/types.h>
 #include <asm/barrier.h>
 #include <asm/cpu-features.h>
 #include <asm/war.h>
 #include <asm/system.h>
 
-typedef struct { volatile int counter; } atomic_t;
-
 #define ATOMIC_INIT(i)    { (i) }
 
 /*
@@ -51,7 +50,7 @@ typedef struct { volatile int counter; } atomic_t;
 static __inline__ void atomic_add(int i, atomic_t * v)
 {
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -63,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -96,7 +95,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
 static __inline__ void atomic_sub(int i, atomic_t * v)
 {
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -108,7 +107,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -136,12 +135,12 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
  */
 static __inline__ int atomic_add_return(int i, atomic_t * v)
 {
-       unsigned long result;
+       int result;
 
        smp_llsc_mb();
 
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -155,7 +154,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
                : "Ir" (i), "m" (v->counter)
                : "memory");
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -188,12 +187,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
 
 static __inline__ int atomic_sub_return(int i, atomic_t * v)
 {
-       unsigned long result;
+       int result;
 
        smp_llsc_mb();
 
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -207,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                : "Ir" (i), "m" (v->counter)
                : "memory");
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -248,12 +247,12 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
  */
 static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 {
-       unsigned long result;
+       int result;
 
        smp_llsc_mb();
 
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -271,7 +270,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                : "Ir" (i), "m" (v->counter)
                : "memory");
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               int temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -404,8 +403,6 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
 
 #ifdef CONFIG_64BIT
 
-typedef struct { volatile long counter; } atomic64_t;
-
 #define ATOMIC64_INIT(i)    { (i) }
 
 /*
@@ -432,7 +429,7 @@ typedef struct { volatile long counter; } atomic64_t;
 static __inline__ void atomic64_add(long i, atomic64_t * v)
 {
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -444,7 +441,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -477,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
 static __inline__ void atomic64_sub(long i, atomic64_t * v)
 {
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -489,7 +486,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
                : "=&r" (temp), "=m" (v->counter)
                : "Ir" (i), "m" (v->counter));
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -517,12 +514,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
  */
 static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 {
-       unsigned long result;
+       long result;
 
        smp_llsc_mb();
 
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -536,7 +533,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
                : "Ir" (i), "m" (v->counter)
                : "memory");
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -569,12 +566,12 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 
 static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 {
-       unsigned long result;
+       long result;
 
        smp_llsc_mb();
 
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -588,7 +585,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
                : "Ir" (i), "m" (v->counter)
                : "memory");
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -629,12 +626,12 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
  */
 static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
 {
-       unsigned long result;
+       long result;
 
        smp_llsc_mb();
 
        if (cpu_has_llsc && R10000_LLSC_WAR) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"
@@ -652,7 +649,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                : "Ir" (i), "m" (v->counter)
                : "memory");
        } else if (cpu_has_llsc) {
-               unsigned long temp;
+               long temp;
 
                __asm__ __volatile__(
                "       .set    mips3                                   \n"