Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/shaggy...

[linux-2.6-omap-h63xx.git] / arch / mips / kernel / ptrace32.c

diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 0c82b25d8c6d17c087f5c3ec0c704052dbd22bd3..f40ecd8be05fc7b5376a4b24856d9236f17fb5c2 100644 (file)
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -88,7 +88,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                ret = -EIO;
                if (copied != sizeof(tmp))
                        break;
-               ret = put_user(tmp, (unsigned int *) (unsigned long) data);
+               ret = put_user(tmp, (unsigned int __user *) (unsigned long) data);
                break;
        }
 
@@ -166,16 +166,25 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                        tmp = regs->lo;
                        break;
                case FPC_CSR:
-                       if (cpu_has_fpu)
-                               tmp = child->thread.fpu.hard.fcr31;
-                       else
-                               tmp = child->thread.fpu.soft.fcr31;
+                       tmp = child->thread.fpu.fcr31;
                        break;
                case FPC_EIR: { /* implementation / version register */
                        unsigned int flags;
+#ifdef CONFIG_MIPS_MT_SMTC
+                       unsigned int irqflags;
+                       unsigned int mtflags;
+#endif /* CONFIG_MIPS_MT_SMTC */
 
-                       if (!cpu_has_fpu)
+                       if (!cpu_has_fpu) {
+                               tmp = 0;
                                break;
+                       }
+
+#ifdef CONFIG_MIPS_MT_SMTC
+                       /* Read-modify-write of Status must be atomic */
+                       local_irq_save(irqflags);
+                       mtflags = dmt();
+#endif /* CONFIG_MIPS_MT_SMTC */
 
                        preempt_disable();
                        if (cpu_has_mipsmt) {
@@ -191,18 +200,25 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
                                write_c0_status(flags);
                        }
+#ifdef CONFIG_MIPS_MT_SMTC
+                       emt(mtflags);
+                       local_irq_restore(irqflags);
+#endif /* CONFIG_MIPS_MT_SMTC */
                        preempt_enable();
                        break;
                }
-               case DSP_BASE ... DSP_BASE + 5:
+               case DSP_BASE ... DSP_BASE + 5: {
+                       dspreg_t *dregs;
+
                        if (!cpu_has_dsp) {
                                tmp = 0;
                                ret = -EIO;
                                goto out_tsk;
                        }
-                       dspreg_t *dregs = __get_dsp_regs(child);
+                       dregs = __get_dsp_regs(child);
                        tmp = (unsigned long) (dregs[addr - DSP_BASE]);
                        break;
+               }
                case DSP_CONTROL:
                        if (!cpu_has_dsp) {
                                tmp = 0;
@@ -216,7 +232,7 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                        ret = -EIO;
                        goto out_tsk;
                }
-               ret = put_user(tmp, (unsigned *) (unsigned long) data);
+               ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
                break;
        }
 
@@ -269,9 +285,9 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
 
                        if (!tsk_used_math(child)) {
                                /* FP not yet used  */
-                               memset(&child->thread.fpu.hard, ~0,
-                                      sizeof(child->thread.fpu.hard));
-                               child->thread.fpu.hard.fcr31 = 0;
+                               memset(&child->thread.fpu, ~0,
+                                      sizeof(child->thread.fpu));
+                               child->thread.fpu.fcr31 = 0;
                        }
                        /*
                         * The odd registers are actually the high order bits
@@ -299,20 +315,20 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                        regs->lo = data;
                        break;
                case FPC_CSR:
-                       if (cpu_has_fpu)
-                               child->thread.fpu.hard.fcr31 = data;
-                       else
-                               child->thread.fpu.soft.fcr31 = data;
+                       child->thread.fpu.fcr31 = data;
                        break;
-               case DSP_BASE ... DSP_BASE + 5:
+               case DSP_BASE ... DSP_BASE + 5: {
+                       dspreg_t *dregs;
+
                        if (!cpu_has_dsp) {
                                ret = -EIO;
                                break;
                        }
 
-                       dspreg_t *dregs = __get_dsp_regs(child);
+                       dregs = __get_dsp_regs(child);
                        dregs[addr - DSP_BASE] = data;
                        break;
+               }
                case DSP_CONTROL:
                        if (!cpu_has_dsp) {
                                ret = -EIO;