void * emulpc, *contpc;
unsigned int cond;
- if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) {
+ if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
fpuemustats.errors++;
return SIGBUS;
}
#endif
return SIGILL;
}
- if (get_user(ir, (mips_instruction *) emulpc)) {
+ if (get_user(ir, (mips_instruction __user *) emulpc)) {
fpuemustats.errors++;
return SIGBUS;
}
emul:
fpuemustats.emulated++;
switch (MIPSInst_OPCODE(ir)) {
-#ifndef SINGLE_ONLY_FPU
case ldc1_op:{
- u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
+ u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
MIPSInst_SIMM(ir));
u64 val;
}
case sdc1_op:{
- u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
+ u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
MIPSInst_SIMM(ir));
u64 val;
}
break;
}
-#endif
case lwc1_op:{
- u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
+ u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
MIPSInst_SIMM(ir));
u32 val;
fpuemustats.errors++;
return SIGBUS;
}
-#ifdef SINGLE_ONLY_FPU
- if (MIPSInst_RT(ir) & 1) {
- /* illegal register in single-float mode */
- return SIGILL;
- }
-#endif
SITOREG(val, MIPSInst_RT(ir));
break;
}
case swc1_op:{
- u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
+ u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
MIPSInst_SIMM(ir));
u32 val;
fpuemustats.stores++;
-#ifdef SINGLE_ONLY_FPU
- if (MIPSInst_RT(ir) & 1) {
- /* illegal register in single-float mode */
- return SIGILL;
- }
-#endif
SIFROMREG(val, MIPSInst_RT(ir));
if (put_user(val, va)) {
fpuemustats.errors++;
case cop1_op:
switch (MIPSInst_RS(ir)) {
-#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
+#if defined(__mips64)
case dmfc_op:
/* copregister fs -> gpr[rt] */
if (MIPSInst_RT(ir) != 0) {
case mfc_op:
/* copregister rd -> gpr[rt] */
-#ifdef SINGLE_ONLY_FPU
- if (MIPSInst_RD(ir) & 1) {
- /* illegal register in single-float mode */
- return SIGILL;
- }
-#endif
if (MIPSInst_RT(ir) != 0) {
SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
MIPSInst_RD(ir));
case mtc_op:
/* copregister rd <- rt */
-#ifdef SINGLE_ONLY_FPU
- if (MIPSInst_RD(ir) & 1) {
- /* illegal register in single-float mode */
- return SIGILL;
- }
-#endif
SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
break;
(xcp->cp0_epc +
(MIPSInst_SIMM(ir) << 2));
- if (get_user(ir, (mips_instruction *)
- (void *) xcp->cp0_epc)) {
+ if (get_user(ir,
+ (mips_instruction __user *) xcp->cp0_epc)) {
fpuemustats.errors++;
return SIGBUS;
}
switch (MIPSInst_OPCODE(ir)) {
case lwc1_op:
case swc1_op:
-#if (__mips >= 2 || __mips64) && !defined(SINGLE_ONLY_FPU)
+#if (__mips >= 2 || defined(__mips64))
case ldc1_op:
case sdc1_op:
#endif
ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
ieee754sp fd, fr, fs, ft;
- u32 *va;
+ u32 __user *va;
u32 val;
switch (MIPSInst_FUNC(ir)) {
case lwxc1_op:
- va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
+ va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
xcp->regs[MIPSInst_FT(ir)]);
fpuemustats.loads++;
fpuemustats.errors++;
return SIGBUS;
}
-#ifdef SINGLE_ONLY_FPU
- if (MIPSInst_FD(ir) & 1) {
- /* illegal register in single-float
- * mode
- */
- return SIGILL;
- }
-#endif
SITOREG(val, MIPSInst_FD(ir));
break;
case swxc1_op:
- va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
+ va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
xcp->regs[MIPSInst_FT(ir)]);
fpuemustats.stores++;
-#ifdef SINGLE_ONLY_FPU
- if (MIPSInst_FS(ir) & 1) {
- /* illegal register in single-float
- * mode
- */
- return SIGILL;
- }
-#endif
SIFROMREG(val, MIPSInst_FS(ir));
if (put_user(val, va)) {
break;
}
-#ifndef SINGLE_ONLY_FPU
case d_fmt:{ /* 1 */
ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
ieee754dp fd, fr, fs, ft;
- u64 *va;
+ u64 __user *va;
u64 val;
switch (MIPSInst_FUNC(ir)) {
case ldxc1_op:
- va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
+ va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
xcp->regs[MIPSInst_FT(ir)]);
fpuemustats.loads++;
break;
case sdxc1_op:
- va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
+ va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
xcp->regs[MIPSInst_FT(ir)]);
fpuemustats.stores++;
}
break;
}
-#endif
case 0x7: /* 7 */
if (MIPSInst_FUNC(ir) != pfetch_op) {
goto scopbop;
/* unary ops */
-#if __mips >= 2 || __mips64
+#if __mips >= 2 || defined(__mips64)
case fsqrt_op:
handler.u = ieee754sp_sqrt;
goto scopuop;
case fcvts_op:
return SIGILL; /* not defined */
case fcvtd_op:{
-#ifdef SINGLE_ONLY_FPU
- return SIGILL; /* not defined */
-#else
ieee754sp fs;
SPFROMREG(fs, MIPSInst_FS(ir));
rfmt = d_fmt;
goto copcsr;
}
-#endif
case fcvtw_op:{
ieee754sp fs;
goto copcsr;
}
-#if __mips >= 2 || __mips64
+#if __mips >= 2 || defined(__mips64)
case fround_op:
case ftrunc_op:
case fceil_op:
}
#endif /* __mips >= 2 */
-#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
+#if defined(__mips64)
case fcvtl_op:{
ieee754sp fs;
rfmt = l_fmt;
goto copcsr;
}
-#endif /* __mips64 && !fpu(single) */
+#endif /* defined(__mips64) */
default:
if (MIPSInst_FUNC(ir) >= fcmp_op) {
break;
}
-#ifndef SINGLE_ONLY_FPU
case d_fmt:{
union {
ieee754dp(*b) (ieee754dp, ieee754dp);
goto dcopbop;
/* unary ops */
-#if __mips >= 2 || __mips64
+#if __mips >= 2 || defined(__mips64)
case fsqrt_op:
handler.u = ieee754dp_sqrt;
goto dcopuop;
goto copcsr;
}
-#if __mips >= 2 || __mips64
+#if __mips >= 2 || defined(__mips64)
case fround_op:
case ftrunc_op:
case fceil_op:
}
#endif
-#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
+#if defined(__mips64)
case fcvtl_op:{
ieee754dp fs;
rfmt = l_fmt;
goto copcsr;
}
-#endif /* __mips >= 3 && !fpu(single) */
+#endif /* __mips >= 3 */
default:
if (MIPSInst_FUNC(ir) >= fcmp_op) {
}
break;
}
-#endif /* ifndef SINGLE_ONLY_FPU */
case w_fmt:{
ieee754sp fs;
rv.s = ieee754sp_fint(fs.bits);
rfmt = s_fmt;
goto copcsr;
-#ifndef SINGLE_ONLY_FPU
case fcvtd_op:
/* convert word to double precision real */
SPFROMREG(fs, MIPSInst_FS(ir));
rv.d = ieee754dp_fint(fs.bits);
rfmt = d_fmt;
goto copcsr;
-#endif
default:
return SIGILL;
}
break;
}
-#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
+#if defined(__mips64)
case l_fmt:{
switch (MIPSInst_FUNC(ir)) {
case fcvts_op:
ctx->fcr31 &= ~cond;
break;
}
-#ifndef SINGLE_ONLY_FPU
case d_fmt:
DPTOREG(rv.d, MIPSInst_FD(ir));
break;
-#endif
case s_fmt:
SPTOREG(rv.s, MIPSInst_FD(ir));
break;
case w_fmt:
SITOREG(rv.w, MIPSInst_FD(ir));
break;
-#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
+#if defined(__mips64)
case l_fmt:
DITOREG(rv.l, MIPSInst_FD(ir));
break;
return 0;
}
-int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
+int fpu_emulator_cop1Handler(struct pt_regs *xcp,
struct mips_fpu_soft_struct *ctx)
{
unsigned long oldepc, prevepc;
do {
prevepc = xcp->cp0_epc;
- if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) {
+ if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
fpuemustats.errors++;
return SIGBUS;
}