x86, ptrace: rlimit BTS buffer allocation

[linux-2.6-omap-h63xx.git] / arch / mips / mm / c-r4k.c

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 971f6c047b8a08426adb88e43567f4ae0343051b..02bd180f0e02748354383af23352900da6d1b02b 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -7,6 +7,7 @@
  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  */
+#include <linux/hardirq.h>
 #include <linux/init.h>
 #include <linux/highmem.h>
 #include <linux/kernel.h>
@@ -345,11 +346,26 @@ static void r4k___flush_cache_all(void)
        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
 }
 
+static inline int has_valid_asid(const struct mm_struct *mm)
+{
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
+       int i;
+
+       for_each_online_cpu(i)
+               if (cpu_context(i, mm))
+                       return 1;
+
+       return 0;
+#else
+       return cpu_context(smp_processor_id(), mm);
+#endif
+}
+
 static inline void local_r4k_flush_cache_range(void * args)
 {
        struct vm_area_struct *vma = args;
 
-       if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
+       if (!(has_valid_asid(vma->vm_mm)))
                return;
 
        r4k_blast_dcache();
@@ -368,7 +384,7 @@ static inline void local_r4k_flush_cache_mm(void * args)
 {
        struct mm_struct *mm = args;
 
-       if (!cpu_context(smp_processor_id(), mm))
+       if (!has_valid_asid(mm))
                return;
 
        /*
@@ -420,7 +436,7 @@ static inline void local_r4k_flush_cache_page(void *args)
         * If ownes no valid ASID yet, cannot possibly have gotten
         * this page into the cache.
         */
-       if (cpu_context(smp_processor_id(), mm) == 0)
+       if (!has_valid_asid(mm))
                return;
 
        addr &= PAGE_MASK;
@@ -433,7 +449,7 @@ static inline void local_r4k_flush_cache_page(void *args)
         * If the page isn't marked valid, the page cannot possibly be
         * in the cache.
         */
-       if (!(pte_val(*ptep) & _PAGE_PRESENT))
+       if (!(pte_present(*ptep)))
                return;
 
        if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
@@ -452,8 +468,6 @@ static inline void local_r4k_flush_cache_page(void *args)
 
        if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
                r4k_blast_dcache_page(addr);
-               if (exec && !cpu_icache_snoops_remote_store)
-                       r4k_blast_scache_page(addr);
        }
        if (exec) {
                if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
@@ -492,7 +506,11 @@ static inline void local_r4k_flush_data_cache_page(void * addr)
 
 static void r4k_flush_data_cache_page(unsigned long addr)
 {
-       r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
+       if (in_atomic())
+               local_r4k_flush_data_cache_page((void *)addr);
+       else
+               r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
+                               1, 1);
 }
 
 struct flush_icache_range_args {
@@ -513,13 +531,6 @@ static inline void local_r4k_flush_icache_range(void *args)
                        R4600_HIT_CACHEOP_WAR_IMPL;
                        protected_blast_dcache_range(start, end);
                }
-
-               if (!cpu_icache_snoops_remote_store && scache_size) {
-                       if (end - start > scache_size)
-                               r4k_blast_scache();
-                       else
-                               protected_blast_scache_range(start, end);
-               }
        }
 
        if (end - start > icache_size)
@@ -578,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                if (size >= scache_size)
                        r4k_blast_scache();
                else
-                       blast_scache_range(addr, addr + size);
+                       blast_inv_scache_range(addr, addr + size);
                return;
        }
 
@@ -586,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                r4k_blast_dcache();
        } else {
                R4600_HIT_CACHEOP_WAR_IMPL;
-               blast_dcache_range(addr, addr + size);
+               blast_inv_dcache_range(addr, addr + size);
        }
 
        bc_inv(addr, size);
@@ -969,6 +980,8 @@ static void __init probe_pcache(void)
        case CPU_AU1100:
        case CPU_AU1550:
        case CPU_AU1200:
+       case CPU_AU1210:
+       case CPU_AU1250:
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
                break;
        }
@@ -983,11 +996,15 @@ static void __init probe_pcache(void)
 
        printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
               icache_size >> 10,
-              cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
+              cpu_has_vtag_icache ? "VIVT" : "VIPT",
               way_string[c->icache.ways], c->icache.linesz);
 
-       printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
-              dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
+       printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+              dcache_size >> 10, way_string[c->dcache.ways],
+              (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
+              (c->dcache.flags & MIPS_CACHE_ALIASES) ?
+                       "cache aliases" : "no aliases",
+              c->dcache.linesz);
 }
 
 /*