Merge branches 'timers/clocksource', 'timers/hrtimers', 'timers/nohz', 'timers/ntp...

[linux-2.6-omap-h63xx.git] / arch / mips / pci / fixup-cobalt.c

diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 75a01e7648985c2cf20a84b5f76a4b13c03e6d43..9553b14002dda51a757cf06ccb0bca5483b86c1a 100644 (file)
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -17,9 +17,25 @@
 #include <asm/io.h>
 #include <asm/gt64120.h>
 
-#include <asm/mach-cobalt/cobalt.h>
+#include <cobalt.h>
+#include <irq.h>
 
-extern int cobalt_board_id;
+/*
+ * PCI slot numbers
+ */
+#define COBALT_PCICONF_CPU     0x06
+#define COBALT_PCICONF_ETH0    0x07
+#define COBALT_PCICONF_RAQSCSI 0x08
+#define COBALT_PCICONF_VIA     0x09
+#define COBALT_PCICONF_PCISLOT 0x0A
+#define COBALT_PCICONF_ETH1    0x0C
+
+/*
+ * The Cobalt board ID information.  The boards have an ID number wired
+ * into the VIA that is available in the high nibble of register 94.
+ */
+#define VIA_COBALT_BRD_ID_REG  0x94
+#define VIA_COBALT_BRD_REG_to_ID(reg)  ((unsigned char)(reg) >> 4)
 
 static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 {
@@ -60,8 +76,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
 
 static void qube_raq_galileo_fixup(struct pci_dev *dev)
 {
-       unsigned short galileo_id;
-
        if (dev->devfn != PCI_DEVFN(0, 0))
                return;
 
@@ -86,66 +100,84 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
         * Therefore we must set the disconnect/retry cycle values to
         * something sensible when using the new Galileo.
         */
-       pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
-       galileo_id &= 0xff;     /* mask off class info */
 
-       printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
+       printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
 
 #if 0
-       if (galileo_id >= 0x10) {
+       if (dev->revision >= 0x10) {
                /* New Galileo, assumes PCI stop line to VIA is connected. */
-               GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
-       } else if (galileo_id == 0x1 || galileo_id == 0x2)
+               GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
+       } else if (dev->revision == 0x1 || dev->revision == 0x2)
 #endif
        {
                signed int timeo;
                /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
-               timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
+               timeo = GT_READ(GT_PCI0_TOR_OFS);
                /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
-               GALILEO_OUTL(
+               GT_WRITE(GT_PCI0_TOR_OFS,
                        (0xff << 16) |          /* retry count */
                        (0xff << 8) |           /* timeout 1   */
-                       0xff,                   /* timeout 0   */
-                       GT_PCI0_TOR_OFS);
+                       0xff);                  /* timeout 0   */
 
                /* enable PCI retry exceeded interrupt */
-               GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
+               GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
        }
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
         qube_raq_galileo_fixup);
 
+int cobalt_board_id;
+
+static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
+{
+       u8 id;
+       int retval;
+
+       retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
+       if (retval) {
+               panic("Cannot read board ID");
+               return;
+       }
+
+       cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
+
+       printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
+        qube_raq_via_board_id_fixup);
+
 static char irq_tab_qube1[] __initdata = {
   [COBALT_PCICONF_CPU]     = 0,
-  [COBALT_PCICONF_ETH0]    = COBALT_QUBE1_ETH0_IRQ,
-  [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
+  [COBALT_PCICONF_ETH0]    = QUBE1_ETH0_IRQ,
+  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
   [COBALT_PCICONF_VIA]     = 0,
-  [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
+  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
   [COBALT_PCICONF_ETH1]    = 0
 };
 
 static char irq_tab_cobalt[] __initdata = {
   [COBALT_PCICONF_CPU]     = 0,
-  [COBALT_PCICONF_ETH0]    = COBALT_ETH0_IRQ,
-  [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
+  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
+  [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
   [COBALT_PCICONF_VIA]     = 0,
-  [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
-  [COBALT_PCICONF_ETH1]    = COBALT_ETH1_IRQ
+  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
+  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
 };
 
 static char irq_tab_raq2[] __initdata = {
   [COBALT_PCICONF_CPU]     = 0,
-  [COBALT_PCICONF_ETH0]    = COBALT_ETH0_IRQ,
-  [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ,
+  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
+  [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
   [COBALT_PCICONF_VIA]     = 0,
-  [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
-  [COBALT_PCICONF_ETH1]    = COBALT_ETH1_IRQ
+  [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
+  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
 };
 
-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
-       if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
+       if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
                return irq_tab_qube1[slot];
 
        if (cobalt_board_id == COBALT_BRD_ID_RAQ2)