#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/pagemap.h>
-
+#include <linux/sched.h>
#include <asm/pdc.h>
#include <asm/cache.h>
#include <asm/cacheflush.h>
EXPORT_SYMBOL(dcache_stride);
-#if defined(CONFIG_SMP)
/* On some machines (e.g. ones with the Merced bus), there can be
* only a single PxTLB broadcast at a time; this must be guaranteed
* by software. We put a spinlock around all TLB flushes to
* ensure this.
*/
DEFINE_SPINLOCK(pa_tlb_lock);
-EXPORT_SYMBOL(pa_tlb_lock);
-#endif
struct pdc_cache_info cache_info __read_mostly;
#ifndef CONFIG_PA20
}
EXPORT_SYMBOL(flush_cache_all_local);
-/* flushes EVERYTHING (tlb & cache) */
-
-void
-flush_all_caches(void)
-{
- flush_cache_all();
- flush_tlb_all();
-}
-EXPORT_SYMBOL(flush_all_caches);
-
void
update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
{
flush_kernel_dcache_page(page);
clear_bit(PG_dcache_dirty, &page->flags);
- }
+ } else if (parisc_requires_coherency())
+ flush_kernel_dcache_page(page);
}
void
show_cache_info(struct seq_file *m)
{
+ char buf[32];
+
seq_printf(m, "I-cache\t\t: %ld KB\n",
cache_info.ic_size/1024 );
- seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %d-way associative)\n",
+ if (cache_info.dc_loop != 1)
+ snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
+ seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
cache_info.dc_size/1024,
(cache_info.dc_conf.cc_wt ? "WT":"WB"),
(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
- (cache_info.dc_conf.cc_assoc)
- );
-
+ ((cache_info.dc_loop == 1) ? "direct mapped" : buf));
seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
cache_info.it_size,
cache_info.dt_size,
cache_info.dc_conf.cc_block,
cache_info.dc_conf.cc_line,
cache_info.dc_conf.cc_shift);
- printk(" wt %d sh %d cst %d assoc %d\n",
+ printk(" wt %d sh %d cst %d hv %d\n",
cache_info.dc_conf.cc_wt,
cache_info.dc_conf.cc_sh,
cache_info.dc_conf.cc_cst,
- cache_info.dc_conf.cc_assoc);
+ cache_info.dc_conf.cc_hv);
printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
cache_info.ic_base,
cache_info.ic_conf.cc_block,
cache_info.ic_conf.cc_line,
cache_info.ic_conf.cc_shift);
- printk(" wt %d sh %d cst %d assoc %d\n",
+ printk(" wt %d sh %d cst %d hv %d\n",
cache_info.ic_conf.cc_wt,
cache_info.ic_conf.cc_sh,
cache_info.ic_conf.cc_cst,
- cache_info.ic_conf.cc_assoc);
+ cache_info.ic_conf.cc_hv);
printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
cache_info.dt_conf.tc_sh,
void disable_sr_hashing(void)
{
- int srhash_type;
+ int srhash_type, retval;
+ unsigned long space_bits;
switch (boot_cpu_data.cpu_type) {
case pcx: /* We shouldn't get this far. setup.c should prevent it. */
}
disable_sr_hashing_asm(srhash_type);
+
+ retval = pdc_spaceid_bits(&space_bits);
+ /* If this procedure isn't implemented, don't panic. */
+ if (retval < 0 && retval != PDC_BAD_OPTION)
+ panic("pdc_spaceid_bits call failed.\n");
+ if (space_bits != 0)
+ panic("SpaceID hashing is still on!\n");
+}
+
+/* Simple function to work out if we have an existing address translation
+ * for a user space vma. */
+static inline int translation_exists(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long pfn)
+{
+ pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
+ pmd_t *pmd;
+ pte_t pte;
+
+ if(pgd_none(*pgd))
+ return 0;
+
+ pmd = pmd_offset(pgd, addr);
+ if(pmd_none(*pmd) || pmd_bad(*pmd))
+ return 0;
+
+ /* We cannot take the pte lock here: flush_cache_page is usually
+ * called with pte lock already held. Whereas flush_dcache_page
+ * takes flush_dcache_mmap_lock, which is lower in the hierarchy:
+ * the vma itself is secure, but the pte might come or go racily.
+ */
+ pte = *pte_offset_map(pmd, addr);
+ /* But pte_unmap() does nothing on this architecture */
+
+ /* Filter out coincidental file entries and swap entries */
+ if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
+ return 0;
+
+ return pte_pfn(pte) == pfn;
+}
+
+/* Private function to flush a page from the cache of a non-current
+ * process. cr25 contains the Page Directory of the current user
+ * process; we're going to hijack both it and the user space %sr3 to
+ * temporarily make the non-current process current. We have to do
+ * this because cache flushing may cause a non-access tlb miss which
+ * the handlers have to fill in from the pgd of the non-current
+ * process. */
+static inline void
+flush_user_cache_page_non_current(struct vm_area_struct *vma,
+ unsigned long vmaddr)
+{
+ /* save the current process space and pgd */
+ unsigned long space = mfsp(3), pgd = mfctl(25);
+
+ /* we don't mind taking interrups since they may not
+ * do anything with user space, but we can't
+ * be preempted here */
+ preempt_disable();
+
+ /* make us current */
+ mtctl(__pa(vma->vm_mm->pgd), 25);
+ mtsp(vma->vm_mm->context, 3);
+
+ flush_user_dcache_page(vmaddr);
+ if(vma->vm_flags & VM_EXEC)
+ flush_user_icache_page(vmaddr);
+
+ /* put the old current process back */
+ mtsp(space, 3);
+ mtctl(pgd, 25);
+ preempt_enable();
+}
+
+
+static inline void
+__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
+{
+ if (likely(vma->vm_mm->context == mfsp(3))) {
+ flush_user_dcache_page(vmaddr);
+ if (vma->vm_flags & VM_EXEC)
+ flush_user_icache_page(vmaddr);
+ } else {
+ flush_user_cache_page_non_current(vma, vmaddr);
+ }
}
void flush_dcache_page(struct page *page)
#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
-void parisc_setup_cache_timing(void)
+void __init parisc_setup_cache_timing(void)
{
unsigned long rangetime, alltime;
unsigned long size;
if (!parisc_cache_flush_threshold)
parisc_cache_flush_threshold = FLUSH_THRESHOLD;
+ if (parisc_cache_flush_threshold > cache_info.dc_size)
+ parisc_cache_flush_threshold = cache_info.dc_size;
+
printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
}
+
+extern void purge_kernel_dcache_page(unsigned long);
+extern void clear_user_page_asm(void *page, unsigned long vaddr);
+
+void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
+{
+ purge_kernel_dcache_page((unsigned long)page);
+ purge_tlb_start();
+ pdtlb_kernel(page);
+ purge_tlb_end();
+ clear_user_page_asm(page, vaddr);
+}
+EXPORT_SYMBOL(clear_user_page);
+
+void flush_kernel_dcache_page_addr(void *addr)
+{
+ flush_kernel_dcache_page_asm(addr);
+ purge_tlb_start();
+ pdtlb_kernel(addr);
+ purge_tlb_end();
+}
+EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
+
+void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
+ struct page *pg)
+{
+ /* no coherency needed (all in kmap/kunmap) */
+ copy_user_page_asm(vto, vfrom);
+ if (!parisc_requires_coherency())
+ flush_kernel_dcache_page_asm(vto);
+}
+EXPORT_SYMBOL(copy_user_page);
+
+#ifdef CONFIG_PA8X00
+
+void kunmap_parisc(void *addr)
+{
+ if (parisc_requires_coherency())
+ flush_kernel_dcache_page_addr(addr);
+}
+EXPORT_SYMBOL(kunmap_parisc);
+#endif
+
+void __flush_tlb_range(unsigned long sid, unsigned long start,
+ unsigned long end)
+{
+ unsigned long npages;
+
+ npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+ if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
+ flush_tlb_all();
+ else {
+ mtsp(sid, 1);
+ purge_tlb_start();
+ if (split_tlb) {
+ while (npages--) {
+ pdtlb(start);
+ pitlb(start);
+ start += PAGE_SIZE;
+ }
+ } else {
+ while (npages--) {
+ pdtlb(start);
+ start += PAGE_SIZE;
+ }
+ }
+ purge_tlb_end();
+ }
+}
+
+static void cacheflush_h_tmp_function(void *dummy)
+{
+ flush_cache_all_local();
+}
+
+void flush_cache_all(void)
+{
+ on_each_cpu(cacheflush_h_tmp_function, NULL, 1, 1);
+}
+
+void flush_cache_mm(struct mm_struct *mm)
+{
+#ifdef CONFIG_SMP
+ flush_cache_all();
+#else
+ flush_cache_all_local();
+#endif
+}
+
+void
+flush_user_dcache_range(unsigned long start, unsigned long end)
+{
+ if ((end - start) < parisc_cache_flush_threshold)
+ flush_user_dcache_range_asm(start,end);
+ else
+ flush_data_cache();
+}
+
+void
+flush_user_icache_range(unsigned long start, unsigned long end)
+{
+ if ((end - start) < parisc_cache_flush_threshold)
+ flush_user_icache_range_asm(start,end);
+ else
+ flush_instruction_cache();
+}
+
+
+void flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ int sr3;
+
+ if (!vma->vm_mm->context) {
+ BUG();
+ return;
+ }
+
+ sr3 = mfsp(3);
+ if (vma->vm_mm->context == sr3) {
+ flush_user_dcache_range(start,end);
+ flush_user_icache_range(start,end);
+ } else {
+ flush_cache_all();
+ }
+}
+
+void
+flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
+{
+ BUG_ON(!vma->vm_mm->context);
+
+ if (likely(translation_exists(vma, vmaddr, pfn)))
+ __flush_cache_page(vma, vmaddr);
+
+}
projects / linux-2.6-omap-h63xx.git / blobdiff