*/
#ifdef CONFIG_64BIT
-#define ADDIB addib,*
-#define CMPB cmpb,*
-#define ANDCM andcm,*
-
.level 2.0w
#else
-#define ADDIB addib,
-#define CMPB cmpb,
-#define ANDCM andcm
-
.level 2.0
#endif
-#include <linux/config.h>
-
#include <asm/psw.h>
#include <asm/assembly.h>
#include <asm/pgtable.h>
#include <asm/cache.h>
+#include <linux/linkage.h>
.text
.align 128
- .export flush_tlb_all_local,code
-
-flush_tlb_all_local:
+ENTRY(flush_tlb_all_local)
.proc
.callinfo NO_CALLS
.entry
*/
/* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
- rsm PSW_SM_I, %r19 /* save I-bit state */
+ rsm PSW_SM_I, %r19 /* save I-bit state */
load32 PA(1f), %r1
nop
nop
rfi
nop
-1: ldil L%PA(cache_info), %r1
- ldo R%PA(cache_info)(%r1), %r1
+1: load32 PA(cache_info), %r1
/* Flush Instruction Tlb */
.exit
.procend
+ENDPROC(flush_tlb_all_local)
- .export flush_instruction_cache_local,code
.import cache_info,data
-flush_instruction_cache_local:
+ENTRY(flush_instruction_cache_local)
.proc
.callinfo NO_CALLS
.entry
mtsp %r0, %sr1
- ldil L%cache_info, %r1
- ldo R%cache_info(%r1), %r1
+ load32 cache_info, %r1
/* Flush Instruction Cache */
.exit
.procend
+ENDPROC(flush_instruction_cache_local)
- .export flush_data_cache_local, code
- .import cache_info, data
-flush_data_cache_local:
+ .import cache_info, data
+ENTRY(flush_data_cache_local)
.proc
.callinfo NO_CALLS
.entry
mtsp %r0, %sr1
- ldil L%cache_info, %r1
- ldo R%cache_info(%r1), %r1
+ load32 cache_info, %r1
/* Flush Data Cache */
.exit
.procend
+ENDPROC(flush_data_cache_local)
- .export copy_user_page_asm,code
.align 16
-copy_user_page_asm:
+ENTRY(copy_user_page_asm)
.proc
.callinfo NO_CALLS
.entry
*/
ldd 0(%r25), %r19
- ldi 32, %r1 /* PAGE_SIZE/128 == 32 */
+ ldi ASM_PAGE_SIZE_DIV128, %r1
+
ldw 64(%r25), %r0 /* prefetch 1 cacheline ahead */
ldw 128(%r25), %r0 /* prefetch 2 */
* use ldd/std on a 32 bit kernel.
*/
ldw 0(%r25), %r19
- ldi 64, %r1 /* PAGE_SIZE/64 == 64 */
+ ldi ASM_PAGE_SIZE_DIV64, %r1
1:
ldw 4(%r25), %r20
.exit
.procend
+ENDPROC(copy_user_page_asm)
/*
* NOTE: Code in clear_user_page has a hard coded dependency on the
* lobby for such a change.
*/
- .export copy_user_page_asm,code
-
-copy_user_page_asm:
+ENTRY(copy_user_page_asm)
.proc
.callinfo NO_CALLS
.entry
sub %r25, %r1, %r23 /* move physical addr into non shadowed reg */
ldil L%(TMPALIAS_MAP_START), %r28
+ /* FIXME for different page sizes != 4k */
#ifdef CONFIG_64BIT
extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
.exit
.procend
+ENDPROC(copy_user_page_asm)
#endif
- .export __clear_user_page_asm,code
-
-__clear_user_page_asm:
+ENTRY(__clear_user_page_asm)
.proc
.callinfo NO_CALLS
.entry
#ifdef CONFIG_64BIT
#if (TMPALIAS_MAP_START >= 0x80000000)
depdi 0, 31,32, %r28 /* clear any sign extension */
+ /* FIXME: page size dependend */
#endif
extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
pdtlb 0(%r28)
#ifdef CONFIG_64BIT
- ldi 32, %r1 /* PAGE_SIZE/128 == 32 */
+ ldi ASM_PAGE_SIZE_DIV128, %r1
/* PREFETCH (Write) has not (yet) been proven to help here */
-/* #define PREFETCHW_OP ldd 256(%0), %r0 */
+ /* #define PREFETCHW_OP ldd 256(%0), %r0 */
1: std %r0, 0(%r28)
std %r0, 8(%r28)
ldo 128(%r28), %r28
#else /* ! CONFIG_64BIT */
-
- ldi 64, %r1 /* PAGE_SIZE/64 == 64 */
+ ldi ASM_PAGE_SIZE_DIV64, %r1
1:
stw %r0, 0(%r28)
.exit
.procend
+ENDPROC(__clear_user_page_asm)
- .export flush_kernel_dcache_page
-
-flush_kernel_dcache_page:
+ENTRY(flush_kernel_dcache_page_asm)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(flush_kernel_dcache_page_asm)
- .export flush_user_dcache_page
-
-flush_user_dcache_page:
+ENTRY(flush_user_dcache_page)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(flush_user_dcache_page)
- .export flush_user_icache_page
-
-flush_user_icache_page:
+ENTRY(flush_user_icache_page)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(flush_user_icache_page)
- .export purge_kernel_dcache_page
-
-purge_kernel_dcache_page:
+ENTRY(purge_kernel_dcache_page)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(purge_kernel_dcache_page)
#if 0
/* Currently not used, but it still is a possible alternate
* solution.
*/
- .export flush_alias_page
-
-flush_alias_page:
+ENTRY(flush_alias_page)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(flush_alias_page)
- .export flush_kernel_dcache_range_asm
-
-flush_kernel_dcache_range_asm:
+ENTRY(flush_kernel_dcache_range_asm)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(flush_kernel_dcache_range_asm)
- .export flush_user_icache_range_asm
-
-flush_user_icache_range_asm:
+ENTRY(flush_user_icache_range_asm)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(flush_user_icache_range_asm)
- .export flush_kernel_icache_page
-
-flush_kernel_icache_page:
+ENTRY(flush_kernel_icache_page)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(flush_kernel_icache_page)
- .export flush_kernel_icache_range_asm
-
-flush_kernel_icache_range_asm:
+ENTRY(flush_kernel_icache_range_asm)
.proc
.callinfo NO_CALLS
.entry
nop
.exit
.procend
+ENDPROC(flush_kernel_icache_range_asm)
/* align should cover use of rfi in disable_sr_hashing_asm and
* srdis_done.
*/
.align 256
- .export disable_sr_hashing_asm,code
-
-disable_sr_hashing_asm:
+ENTRY(disable_sr_hashing_asm)
.proc
.callinfo NO_CALLS
.entry
.exit
.procend
+ENDPROC(disable_sr_hashing_asm)
.end