powerpc: Fallout from sysdev API changes

[linux-2.6-omap-h63xx.git] / arch / powerpc / boot / dcr.h

diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 877bc97b1e975752d8513aa0d54bd80dff3b7baf..95b9f5344016a619d97d413d738dc89394c28511 100644 (file)
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -14,18 +14,63 @@
 #define DCRN_SDRAM0_CFGADDR                            0x010
 #define DCRN_SDRAM0_CFGDATA                            0x011
 
+#define SDRAM0_READ(offset) ({\
+       mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
+       mfdcr(DCRN_SDRAM0_CFGDATA); })
+#define SDRAM0_WRITE(offset, data) ({\
+       mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
+       mtdcr(DCRN_SDRAM0_CFGDATA, data); })
+
 #define        SDRAM0_B0CR                             0x40
 #define        SDRAM0_B1CR                             0x44
 #define        SDRAM0_B2CR                             0x48
 #define        SDRAM0_B3CR                             0x4c
 
-static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
+static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
+                                           SDRAM0_B2CR, SDRAM0_B3CR };
 
 #define                        SDRAM_CONFIG_BANK_ENABLE        0x00000001
 #define                        SDRAM_CONFIG_SIZE_MASK          0x000e0000
 #define                        SDRAM_CONFIG_BANK_SIZE(reg)     \
        (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
 
+/* 440GP External Bus Controller (EBC) */
+#define DCRN_EBC0_CFGADDR                              0x012
+#define DCRN_EBC0_CFGDATA                              0x013
+#define   EBC_NUM_BANKS                                          8
+#define   EBC_B0CR                                       0x00
+#define   EBC_B1CR                                       0x01
+#define   EBC_B2CR                                       0x02
+#define   EBC_B3CR                                       0x03
+#define   EBC_B4CR                                       0x04
+#define   EBC_B5CR                                       0x05
+#define   EBC_B6CR                                       0x06
+#define   EBC_B7CR                                       0x07
+#define   EBC_BXCR(n)                                    (n)
+#define            EBC_BXCR_BAS                                    0xfff00000
+#define            EBC_BXCR_BS                                     0x000e0000
+#define            EBC_BXCR_BANK_SIZE(reg) \
+       (0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
+#define            EBC_BXCR_BU                                     0x00018000
+#define              EBC_BXCR_BU_OFF                                 0x00000000
+#define              EBC_BXCR_BU_RO                                  0x00008000
+#define              EBC_BXCR_BU_WO                                  0x00010000
+#define              EBC_BXCR_BU_RW                                  0x00018000
+#define            EBC_BXCR_BW                                     0x00006000
+#define   EBC_B0AP                                       0x10
+#define   EBC_B1AP                                       0x11
+#define   EBC_B2AP                                       0x12
+#define   EBC_B3AP                                       0x13
+#define   EBC_B4AP                                       0x14
+#define   EBC_B5AP                                       0x15
+#define   EBC_B6AP                                       0x16
+#define   EBC_B7AP                                       0x17
+#define   EBC_BXAP(n)                                    (0x10+(n))
+#define   EBC_BEAR                                       0x20
+#define   EBC_BESR                                       0x21
+#define   EBC_CFG                                        0x23
+#define   EBC_CID                                        0x24
+
 /* 440GP Clock, PM, chip control */
 #define DCRN_CPC0_SR                                   0x0b0
 #define DCRN_CPC0_ER                                   0x0b1
@@ -84,4 +129,71 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C
 #define DCRN_CPC0_MIRQ1                                        0x0ed
 #define DCRN_CPC0_JTAGID                               0x0ef
 
+#define DCRN_MAL0_CFG                                  0x180
+#define MAL_RESET 0x80000000
+
+/* 440EP Clock/Power-on Reset regs */
+#define DCRN_CPR0_ADDR 0xc
+#define DCRN_CPR0_DATA 0xd
+#define CPR0_PLLD0     0x60
+#define CPR0_OPBD0     0xc0
+#define CPR0_PERD0     0xe0
+#define CPR0_PRIMBD0   0xa0
+#define CPR0_SCPID     0x120
+#define CPR0_PLLC0     0x40
+
+/* 405GP Clocking/Power Management/Chip Control regs */
+#define DCRN_CPC0_PLLMR 0xb0
+#define DCRN_405_CPC0_CR0 0xb1
+#define DCRN_405_CPC0_CR1 0xb2
+#define DCRN_405_CPC0_PSR 0xb4
+
+/* 405EP Clocking/Power Management/Chip Control regs */
+#define DCRN_CPC0_PLLMR0  0xf0
+#define DCRN_CPC0_PLLMR1  0xf4
+#define DCRN_CPC0_UCR     0xf5
+
+/* 440GX Clock control etc */
+
+
+#define DCRN_CPR0_CLKUPD                               0x020
+#define DCRN_CPR0_PLLC                                 0x040
+#define DCRN_CPR0_PLLD                                 0x060
+#define DCRN_CPR0_PRIMAD                               0x080
+#define DCRN_CPR0_PRIMBD                               0x0a0
+#define DCRN_CPR0_OPBD                                 0x0c0
+#define DCRN_CPR0_PERD                                 0x0e0
+#define DCRN_CPR0_MALD                                 0x100
+
+#define DCRN_SDR0_CONFIG_ADDR  0xe
+#define DCRN_SDR0_CONFIG_DATA  0xf
+
+/* SDR read/write helper macros */
+#define SDR0_READ(offset) ({\
+       mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
+       mfdcr(DCRN_SDR0_CONFIG_DATA); })
+#define SDR0_WRITE(offset, data) ({\
+       mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
+       mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
+
+#define DCRN_SDR0_UART0                0x0120
+#define DCRN_SDR0_UART1                0x0121
+#define DCRN_SDR0_UART2                0x0122
+#define DCRN_SDR0_UART3                0x0123
+
+
+/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
+
+#define DCRN_CPR0_CFGADDR                              0xc
+#define DCRN_CPR0_CFGDATA                              0xd
+
+#define CPR0_READ(offset) ({\
+       mtdcr(DCRN_CPR0_CFGADDR, offset); \
+       mfdcr(DCRN_CPR0_CFGDATA); })
+#define CPR0_WRITE(offset, data) ({\
+       mtdcr(DCRN_CPR0_CFGADDR, offset); \
+       mtdcr(DCRN_CPR0_CFGDATA, data); })
+
+
+
 #endif /* _PPC_BOOT_DCR_H_ */