Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6

[linux-2.6-omap-h63xx.git] / arch / powerpc / kernel / cpu_setup_44x.S

diff --git a/arch/powerpc/kernel/cpu_setup_44x.S b/arch/powerpc/kernel/cpu_setup_44x.S
index 6a6e6c71ad6f145bea9f251ede0270d0da451b0d..8e1812e2f3ee58648ea46d2afac342641ee491af 100644 (file)
--- a/arch/powerpc/kernel/cpu_setup_44x.S
+++ b/arch/powerpc/kernel/cpu_setup_44x.S
@@ -17,3 +17,40 @@
 #include <asm/cputable.h>
 #include <asm/ppc_asm.h>
 
+_GLOBAL(__setup_cpu_440ep)
+       b       __init_fpu_44x
+_GLOBAL(__setup_cpu_440epx)
+       mflr    r4
+       bl      __init_fpu_44x
+       bl      __plb_disable_wrp
+       mtlr    r4
+       blr
+_GLOBAL(__setup_cpu_440grx)
+       b       __plb_disable_wrp
+
+
+/* enable APU between CPU and FPU */
+_GLOBAL(__init_fpu_44x)
+       mfspr   r3,SPRN_CCR0
+       /* Clear DAPUIB flag in CCR0 */
+       rlwinm  r3,r3,0,12,10
+       mtspr   SPRN_CCR0,r3
+       isync
+       blr
+
+/*
+ * Workaround for the incorrect write to DDR SDRAM errata.
+ * The write address can be corrupted during writes to
+ * DDR SDRAM when write pipelining is enabled on PLB0.
+ * Disable write pipelining here.
+ */
+#define DCRN_PLB4A0_ACR        0x81
+
+_GLOBAL(__plb_disable_wrp)
+       mfdcr   r3,DCRN_PLB4A0_ACR
+       /* clear WRP bit in PLB4A0_ACR */
+       rlwinm  r3,r3,0,8,6
+       mtdcr   DCRN_PLB4A0_ACR,r3
+       isync
+       blr
+