Revert "[POWERPC] Add compat handler for PTRACE_GETSIGINFO"

[linux-2.6-omap-h63xx.git] / arch / powerpc / kernel / misc_32.S

diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 0ed2c7eddc9e848532fcdcf31dab956a184c0a65..9d2c56621f1ea0ad18ee1a0d89e46931ece7e7a5 100644 (file)
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -206,6 +206,45 @@ _GLOBAL(_nmask_and_or_msr)
        isync
        blr                     /* Done */
 
+#ifdef CONFIG_40x
+
+/*
+ * Do an IO access in real mode
+ */
+_GLOBAL(real_readb)
+       mfmsr   r7
+       ori     r0,r7,MSR_DR
+       xori    r0,r0,MSR_DR
+       sync
+       mtmsr   r0
+       sync
+       isync
+       lbz     r3,0(r3)
+       sync
+       mtmsr   r7
+       sync
+       isync
+       blr
+
+       /*
+ * Do an IO access in real mode
+ */
+_GLOBAL(real_writeb)
+       mfmsr   r7
+       ori     r0,r7,MSR_DR
+       xori    r0,r0,MSR_DR
+       sync
+       mtmsr   r0
+       sync
+       isync
+       stb     r3,0(r4)
+       sync
+       mtmsr   r7
+       sync
+       isync
+       blr
+
+#endif /* CONFIG_40x */
 
 /*
  * Flush MMU TLB
@@ -236,12 +275,6 @@ _GLOBAL(_tlbia)
        /* Invalidate all entries in TLB1 */
        li      r3, 0x0c
        tlbivax 0,3
-       /* Invalidate all entries in TLB2 */
-       li      r3, 0x14
-       tlbivax 0,3
-       /* Invalidate all entries in TLB3 */
-       li      r3, 0x1c
-       tlbivax 0,3
        msync
 #ifdef CONFIG_SMP
        tlbsync
@@ -336,12 +369,8 @@ _GLOBAL(_tlbie)
 #elif defined(CONFIG_FSL_BOOKE)
        rlwinm  r4, r3, 0, 0, 19
        ori     r5, r4, 0x08    /* TLBSEL = 1 */
-       ori     r6, r4, 0x10    /* TLBSEL = 2 */
-       ori     r7, r4, 0x18    /* TLBSEL = 3 */
        tlbivax 0, r4
        tlbivax 0, r5
-       tlbivax 0, r6
-       tlbivax 0, r7
        msync
 #if defined(CONFIG_SMP)
        tlbsync
@@ -543,12 +572,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
        addi    r3,r3,L1_CACHE_BYTES
        bdnz    0b
        sync
+#ifndef CONFIG_44x
+       /* We don't flush the icache on 44x. Those have a virtual icache
+        * and we don't have access to the virtual address here (it's
+        * not the page vaddr but where it's mapped in user space). The
+        * flushing of the icache on these is handled elsewhere, when
+        * a change in the address space occurs, before returning to
+        * user space
+        */
        mtctr   r4
 1:     icbi    0,r6
        addi    r6,r6,L1_CACHE_BYTES
        bdnz    1b
        sync
        isync
+#endif /* CONFIG_44x */
        blr
 
 /*
@@ -747,6 +785,21 @@ _GLOBAL(__lshrdi3)
        or      r4,r4,r7        # LSW |= t2
        blr
 
+/*
+ * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
+ * Returns 0 if a < b, 1 if a == b, 2 if a > b.
+ */
+_GLOBAL(__ucmpdi2)
+       cmplw   r3,r5
+       li      r3,1
+       bne     1f
+       cmplw   r4,r6
+       beqlr
+1:     li      r3,0
+       bltlr
+       li      r3,2
+       blr
+
 _GLOBAL(abs)
        srawi   r4,r3,31
        xor     r3,r3,r4
@@ -784,13 +837,6 @@ _GLOBAL(kernel_thread)
        addi    r1,r1,16
        blr
 
-_GLOBAL(kernel_execve)
-       li      r0,__NR_execve
-       sc
-       bnslr
-       neg     r3,r3
-       blr
-
 /*
  * This routine is just here to keep GCC happy - sigh...
  */