[POWERPC] Fix SLB initialization at boot time

[linux-2.6-omap-h63xx.git] / arch / powerpc / mm / slb_low.S

diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 8548dcf8ef8b35b1089c421785079a6116f932b3..cd1a93d4948ca85868dd943a60667f541229a26e 100644 (file)
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -14,7 +14,6 @@
  *  2 of the License, or (at your option) any later version.
  */
 
-#include <linux/config.h>
 #include <asm/processor.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
@@ -22,6 +21,7 @@
 #include <asm/page.h>
 #include <asm/mmu.h>
 #include <asm/pgtable.h>
+#include <asm/firmware.h>
 
 /* void slb_allocate_realmode(unsigned long ea);
  *
@@ -82,31 +82,45 @@ _GLOBAL(slb_miss_kernel_load_io)
        srdi.   r9,r10,USER_ESID_BITS
        bne-    8f                      /* invalid ea bits set */
 
-       /* Figure out if the segment contains huge pages */
-#ifdef CONFIG_HUGETLB_PAGE
-BEGIN_FTR_SECTION
-       b       1f
-END_FTR_SECTION_IFCLR(CPU_FTR_16M_PAGE)
+
+       /* when using slices, we extract the psize off the slice bitmaps
+        * and then we need to get the sllp encoding off the mmu_psize_defs
+        * array.
+        *
+        * XXX This is a bit inefficient especially for the normal case,
+        * so we should try to implement a fast path for the standard page
+        * size using the old sllp value so we avoid the array. We cannot
+        * really do dynamic patching unfortunately as processes might flip
+        * between 4k and 64k standard page size
+        */
+#ifdef CONFIG_PPC_MM_SLICES
        cmpldi  r10,16
 
-       lhz     r9,PACALOWHTLBAREAS(r13)
-       mr      r11,r10
+       /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
+       ld      r9,PACALOWSLICESPSIZE(r13)
+       sldi    r11,r10,2
        blt     5f
+       ld      r9,PACAHIGHSLICEPSIZE(r13)
+       srdi    r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
+       andi.   r11,r11,0x3c
 
-       lhz     r9,PACAHIGHHTLBAREAS(r13)
-       srdi    r11,r10,(HTLB_AREA_SHIFT-SID_SHIFT)
-
-5:     srd     r9,r9,r11
-       andi.   r9,r9,1
-       beq     1f
-_GLOBAL(slb_miss_user_load_huge)
-       li      r11,0
-       b       2f
-1:
-#endif /* CONFIG_HUGETLB_PAGE */
+5:     /* Extract the psize and multiply to get an array offset */
+       srd     r9,r9,r11
+       andi.   r9,r9,0xf
+       mulli   r9,r9,MMUPSIZEDEFSIZE
 
+       /* Now get to the array and obtain the sllp
+        */
+       ld      r11,PACATOC(r13)
+       ld      r11,mmu_psize_defs@got(r11)
+       add     r11,r11,r9
+       ld      r11,MMUPSIZESLLP(r11)
+       ori     r11,r11,SLB_VSID_USER
+#else
+       /* paca context sllp already contains the SLB_VSID_USER bits */
        lhz     r11,PACACONTEXTSLLP(r13)
-2:
+#endif /* CONFIG_PPC_MM_SLICES */
+
        ld      r9,PACACONTEXTID(r13)
        rldimi  r10,r9,USER_ESID_BITS,0
        b       slb_finish_load
@@ -184,6 +198,7 @@ slb_finish_load:
         * dont have any LRU information to help us choose a slot.
         */
 #ifdef CONFIG_PPC_ISERIES
+BEGIN_FW_FTR_SECTION
        /*
         * On iSeries, the "bolted" stack segment can be cast out on
         * shared processor switch so we need to check for a miss on
@@ -195,6 +210,7 @@ slb_finish_load:
        li      r10,SLB_NUM_BOLTED-1    /* Stack goes in last bolted slot */
        cmpld   r9,r3
        beq     3f
+END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif /* CONFIG_PPC_ISERIES */
 
        ld      r10,PACASTABRR(r13)