Merge master.kernel.org:/home/rmk/linux-2.6-mmc

[linux-2.6-omap-h63xx.git] / arch / powerpc / platforms / powermac / nvram.c

diff --git a/arch/powerpc/platforms/powermac/nvram.c b/arch/powerpc/platforms/powermac/nvram.c
index 5fd28995c74ceabb01f0c35792138918003c036a..262f967b880a151ca132df5d6933b01637974cec 100644 (file)
--- a/arch/powerpc/platforms/powermac/nvram.c
+++ b/arch/powerpc/platforms/powermac/nvram.c
@@ -74,7 +74,7 @@ struct core99_header {
  * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
  */
 static int nvram_naddrs;
-static volatile unsigned char *nvram_data;
+static volatile unsigned char __iomem *nvram_data;
 static int is_core_99;
 static int core99_bank = 0;
 static int nvram_partitions[3];
@@ -148,7 +148,7 @@ static ssize_t core99_nvram_size(void)
 }
 
 #ifdef CONFIG_PPC32
-static volatile unsigned char *nvram_addr;
+static volatile unsigned char __iomem *nvram_addr;
 static int nvram_mult;
 
 static unsigned char direct_nvram_read_byte(int addr)
@@ -285,7 +285,7 @@ static int sm_erase_bank(int bank)
        int stat, i;
        unsigned long timeout;
 
-       u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
+       u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 
                DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
 
@@ -317,7 +317,7 @@ static int sm_write_bank(int bank, u8* datas)
        int i, stat = 0;
        unsigned long timeout;
 
-       u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
+       u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 
                DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
 
@@ -352,7 +352,7 @@ static int amd_erase_bank(int bank)
        int i, stat = 0;
        unsigned long timeout;
 
-       u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
+       u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 
                DBG("nvram: AMD Erasing bank %d...\n", bank);
 
@@ -399,7 +399,7 @@ static int amd_write_bank(int bank, u8* datas)
        int i, stat = 0;
        unsigned long timeout;
 
-       u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
+       u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 
                DBG("nvram: AMD Writing bank %d...\n", bank);
 
@@ -597,7 +597,7 @@ int __init pmac_nvram_init(void)
        }
 
 #ifdef CONFIG_PPC32
-       if (_machine == _MACH_chrp && nvram_naddrs == 1) {
+       if (machine_is(chrp) && nvram_naddrs == 1) {
                nvram_data = ioremap(r1.start, s1);
                nvram_mult = 1;
                ppc_md.nvram_read_val   = direct_nvram_read_byte;