sh: Support explicit L1 cache disabling.

[linux-2.6-omap-h63xx.git] / arch / sh / mm / pmb.c

diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index b6a5a338145bf438037f40adfb3142a876a00e1c..7d43758dc2442276fe9391a6b75ac823d1e0454b 100644 (file)
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -145,7 +145,7 @@ repeat:
 
        ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos));
 
-#ifdef CONFIG_SH_WRITETHROUGH
+#ifdef CONFIG_CACHE_WRITETHROUGH
        /*
         * When we are in 32-bit address extended mode, CCR.CB becomes
         * invalid, so care must be taken to manually adjust cacheable
@@ -310,7 +310,7 @@ static int __init pmb_init(void)
        BUG_ON(unlikely(nr_entries >= NR_PMB_ENTRIES));
 
        pmb_cache = kmem_cache_create("pmb", sizeof(struct pmb_entry), 0,
-                                     SLAB_PANIC, pmb_cache_ctor, NULL);
+                                     SLAB_PANIC, pmb_cache_ctor);
 
        jump_to_P2();