Merge branch 'core/rodata' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux...

[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / cpu / amd_64.c

diff --git a/arch/x86/kernel/cpu/amd_64.c b/arch/x86/kernel/cpu/amd_64.c
index 626fc21f027db0d02d68a262bedc436b7f93d623..7c36fb8a28d46455c2a51b8adabc8511e1f9386c 100644 (file)
--- a/arch/x86/kernel/cpu/amd_64.c
+++ b/arch/x86/kernel/cpu/amd_64.c
@@ -6,10 +6,8 @@
 #include <asm/cacheflush.h>
 
 #include <mach_apic.h>
-#include "cpu.h"
 
-extern int __cpuinit get_model_name(struct cpuinfo_x86 *c);
-extern void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c);
+#include "cpu.h"
 
 int force_mwait __cpuinitdata;
 
@@ -110,38 +108,7 @@ static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 #endif
 }
 
-#define ENABLE_C1E_MASK                0x18000000
-#define CPUID_PROCESSOR_SIGNATURE      1
-#define CPUID_XFAM             0x0ff00000
-#define CPUID_XFAM_K8          0x00000000
-#define CPUID_XFAM_10H         0x00100000
-#define CPUID_XFAM_11H         0x00200000
-#define CPUID_XMOD             0x000f0000
-#define CPUID_XMOD_REV_F       0x00040000
-
-/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
-static __cpuinit int amd_apic_timer_broken(void)
-{
-       u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
-
-       switch (eax & CPUID_XFAM) {
-       case CPUID_XFAM_K8:
-               if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
-                       break;
-       case CPUID_XFAM_10H:
-       case CPUID_XFAM_11H:
-               rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
-               if (lo & ENABLE_C1E_MASK)
-                       return 1;
-               break;
-       default:
-               /* err on the side of caution */
-               return 1;
-       }
-       return 0;
-}
-
-void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
+static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 {
        early_init_amd_mc(c);
 
@@ -150,7 +117,7 @@ void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 }
 
-void __cpuinit init_amd(struct cpuinfo_x86 *c)
+static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 {
        unsigned level;
 
@@ -164,7 +131,7 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
         * Errata 63 for SH-B3 steppings
         * Errata 122 for all steppings (F+ have it disabled by default)
         */
-       if (c->x86 == 15) {
+       if (c->x86 == 0xf) {
                rdmsrl(MSR_K8_HWCR, value);
                value |= 1 << 6;
                wrmsrl(MSR_K8_HWCR, value);
@@ -176,10 +143,11 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
        clear_cpu_cap(c, 0*32+31);
 
        /* On C+ stepping K8 rep microcode works well for copy/memset */
-       level = cpuid_eax(1);
-       if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
-                            level >= 0x0f58))
-               set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+       if (c->x86 == 0xf) {
+               level = cpuid_eax(1);
+               if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
+                       set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+       }
        if (c->x86 == 0x10 || c->x86 == 0x11)
                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 
@@ -190,7 +158,7 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
        level = get_model_name(c);
        if (!level) {
                switch (c->x86) {
-               case 15:
+               case 0xf:
                        /* Should distinguish Models here, but this is only
                           a fallback anyways. */
                        strcpy(c->x86_model_id, "Hammer");
@@ -209,20 +177,19 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
        else
                num_cache_leaves = 3;
 
-       if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
+       if (c->x86 >= 0xf && c->x86 <= 0x11)
                set_cpu_cap(c, X86_FEATURE_K8);
 
        /* MFENCE stops RDTSC speculation */
        set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 
-       if (c->x86 == 0x10)
-               fam10h_check_enable_mmcfg();
-
-       if (c->x86 == 0x10)
-               amd_enable_pci_ext_cfg(c);
+       if (c->x86 == 0x10) {
+               /* do this for boot cpu */
+               if (c == &boot_cpu_data)
+                       check_enable_amd_mmconf_dmi();
 
-       if (amd_apic_timer_broken())
-               disable_apic_timer = 1;
+               fam10h_check_enable_mmcfg();
+       }
 
        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
                unsigned long long tseg;
@@ -232,9 +199,24 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 * Don't do it for gbpages because there seems very little
                 * benefit in doing so.
                 */
-               if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
-                   (tseg >> PMD_SHIFT) <
-                       (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
+               if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
+                   printk(KERN_DEBUG "tseg: %010llx\n", tseg);
+                   if ((tseg>>PMD_SHIFT) <
+                               (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
+                       ((tseg>>PMD_SHIFT) <
+                               (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
+                        (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
                        set_memory_4k((unsigned long)__va(tseg), 1);
+               }
        }
 }
+
+static struct cpu_dev amd_cpu_dev __cpuinitdata = {
+       .c_vendor       = "AMD",
+       .c_ident        = { "AuthenticAMD" },
+       .c_early_init   = early_init_amd,
+       .c_init         = init_amd,
+};
+
+cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);
+