x86, fpu: lazy allocation of FPU area - v5

[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / process_64.c

diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 46c4c546b499806fc70aa2788393a9e989106949..891af1a1b48a5cbf0ef303d9f1b5c5601b485869 100644 (file)
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -36,6 +36,7 @@
 #include <linux/kprobes.h>
 #include <linux/kdebug.h>
 #include <linux/tick.h>
+#include <linux/prctl.h>
 
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -107,16 +108,8 @@ void default_idle(void)
        smp_mb();
        local_irq_disable();
        if (!need_resched()) {
-               ktime_t t0, t1;
-               u64 t0n, t1n;
-
-               t0 = ktime_get();
-               t0n = ktime_to_ns(t0);
                safe_halt();    /* enables interrupts racelessly */
                local_irq_disable();
-               t1 = ktime_get();
-               t1n = ktime_to_ns(t1);
-               sched_clock_idle_wakeup_event(t1n - t0n);
        }
        local_irq_enable();
        current_thread_info()->status |= TS_POLLING;
@@ -528,6 +521,83 @@ out:
        return err;
 }
 
+void
+start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
+{
+       asm volatile("movl %0, %%fs; movl %0, %%es; movl %0, %%ds" :: "r"(0));
+       load_gs_index(0);
+       regs->ip                = new_ip;
+       regs->sp                = new_sp;
+       write_pda(oldrsp, new_sp);
+       regs->cs                = __USER_CS;
+       regs->ss                = __USER_DS;
+       regs->flags             = 0x200;
+       set_fs(USER_DS);
+       /*
+        * Free the old FP and other extended state
+        */
+       free_thread_xstate(current);
+}
+EXPORT_SYMBOL_GPL(start_thread);
+
+static void hard_disable_TSC(void)
+{
+       write_cr4(read_cr4() | X86_CR4_TSD);
+}
+
+void disable_TSC(void)
+{
+       preempt_disable();
+       if (!test_and_set_thread_flag(TIF_NOTSC))
+               /*
+                * Must flip the CPU state synchronously with
+                * TIF_NOTSC in the current running context.
+                */
+               hard_disable_TSC();
+       preempt_enable();
+}
+
+static void hard_enable_TSC(void)
+{
+       write_cr4(read_cr4() & ~X86_CR4_TSD);
+}
+
+void enable_TSC(void)
+{
+       preempt_disable();
+       if (test_and_clear_thread_flag(TIF_NOTSC))
+               /*
+                * Must flip the CPU state synchronously with
+                * TIF_NOTSC in the current running context.
+                */
+               hard_enable_TSC();
+       preempt_enable();
+}
+
+int get_tsc_mode(unsigned long adr)
+{
+       unsigned int val;
+
+       if (test_thread_flag(TIF_NOTSC))
+               val = PR_TSC_SIGSEGV;
+       else
+               val = PR_TSC_ENABLE;
+
+       return put_user(val, (unsigned int __user *)adr);
+}
+
+int set_tsc_mode(unsigned int val)
+{
+       if (val == PR_TSC_SIGSEGV)
+               disable_TSC();
+       else if (val == PR_TSC_ENABLE)
+               enable_TSC();
+       else
+               return -EINVAL;
+
+       return 0;
+}
+
 /*
  * This special macro can be used to load a debugging register
  */
@@ -548,12 +618,12 @@ static inline void __switch_to_xtra(struct task_struct *prev_p,
                /* we clear debugctl to make sure DS
                 * is not in use when we change it */
                debugctl = 0;
-               wrmsrl(MSR_IA32_DEBUGCTLMSR, 0);
+               update_debugctlmsr(0);
                wrmsrl(MSR_IA32_DS_AREA, next->ds_area_msr);
        }
 
        if (next->debugctlmsr != debugctl)
-               wrmsrl(MSR_IA32_DEBUGCTLMSR, next->debugctlmsr);
+               update_debugctlmsr(next->debugctlmsr);
 
        if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
                loaddebug(next, 0);
@@ -565,6 +635,15 @@ static inline void __switch_to_xtra(struct task_struct *prev_p,
                loaddebug(next, 7);
        }
 
+       if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
+           test_tsk_thread_flag(next_p, TIF_NOTSC)) {
+               /* prev and next are different */
+               if (test_tsk_thread_flag(next_p, TIF_NOTSC))
+                       hard_disable_TSC();
+               else
+                       hard_enable_TSC();
+       }
+
        if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
                /*
                 * Copy the relevant range of the IO bitmap.
@@ -607,7 +686,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
 
        /* we're going to use this soon, after a few expensive things */
        if (next_p->fpu_counter>5)
-               prefetch(&next->i387.fxsave);
+               prefetch(next->xstate);
 
        /*
         * Reload esp0, LDT and the page table pointer: