Merge git://git.infradead.org/mtd-2.6

[linux-2.6-omap-h63xx.git] / arch / x86 / pci / fixup.c

diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index cb63007e20b2af4142a6cf1703987a48ee86c944..ff3a6a33634231514c945a66f15328a6a8ce534a 100644 (file)
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -17,7 +17,7 @@ static void __devinit pci_fixup_i450nx(struct pci_dev *d)
        int pxb, reg;
        u8 busno, suba, subb;
 
-       printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
+       dev_warn(&d->dev, "Searching for i450NX host bridges\n");
        reg = 0xd0;
        for(pxb = 0; pxb < 2; pxb++) {
                pci_read_config_byte(d, reg++, &busno);
@@ -41,7 +41,7 @@ static void __devinit pci_fixup_i450gx(struct pci_dev *d)
         */
        u8 busno;
        pci_read_config_byte(d, 0x4a, &busno);
-       printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
+       dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
        pci_scan_bus_with_sysdata(busno);
        pcibios_last_bus = -1;
 }
@@ -55,7 +55,7 @@ static void __devinit  pci_fixup_umc_ide(struct pci_dev *d)
         */
        int i;
 
-       printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
+       dev_warn(&d->dev, "Fixing base address flags\n");
        for(i = 0; i < 4; i++)
                d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
 }
@@ -68,7 +68,7 @@ static void __devinit  pci_fixup_ncr53c810(struct pci_dev *d)
         * Fix class to be PCI_CLASS_STORAGE_SCSI
         */
        if (!d->class) {
-               printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
+               dev_warn(&d->dev, "Fixing NCR 53C810 class code\n");
                d->class = PCI_CLASS_STORAGE_SCSI << 8;
        }
 }
@@ -80,7 +80,7 @@ static void __devinit  pci_fixup_latency(struct pci_dev *d)
         *  SiS 5597 and 5598 chipsets require latency timer set to
         *  at most 32 to avoid lockups.
         */
-       DBG("PCI: Setting max latency to 32\n");
+       dev_dbg(&d->dev, "Setting max latency to 32\n");
        pcibios_max_latency = 32;
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
@@ -138,7 +138,7 @@ static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
 
        pci_read_config_byte(d, where, &v);
        if (v & ~mask) {
-               printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
+               dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
                        d->device, d->revision, where, v, mask, v & mask);
                v &= mask;
                pci_write_config_byte(d, where, v);
@@ -200,7 +200,7 @@ static void pci_fixup_nforce2(struct pci_dev *dev)
         * Apply fixup if needed, but don't touch disconnect state
         */
        if ((val & 0x00FF0000) != 0x00010000) {
-               printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
+               dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
                pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
        }
 }
@@ -215,7 +215,8 @@ static int quirk_aspm_offset[MAX_PCIEROOT << 3];
 
 static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
 {
-       return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
+       return raw_pci_read(pci_domain_nr(bus), bus->number,
+                                               devfn, where, size, value);
 }
 
 /*
@@ -231,7 +232,8 @@ static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int wh
        if ((offset) && (where == offset))
                value = value & 0xfffffffc;
 
-       return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
+       return raw_pci_write(pci_domain_nr(bus), bus->number,
+                                               devfn, where, size, value);
 }
 
 static struct pci_ops quirk_pcie_aspm_ops = {
@@ -348,7 +350,7 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
        pci_read_config_word(pdev, PCI_COMMAND, &config);
        if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
                pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
-               printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
+               dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
        }
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
@@ -388,11 +390,11 @@ static void __devinit pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
                /* verify the change for status output */
                pci_read_config_byte(dev, 0x50, &val);
                if (val & 0x40)
-                       printk(KERN_INFO "PCI: Detected MSI K8T Neo2-FIR, "
+                       dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
                                        "can't enable onboard soundcard!\n");
                else
-                       printk(KERN_INFO "PCI: Detected MSI K8T Neo2-FIR, "
-                                       "enabled onboard soundcard.\n");
+                       dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
+                                       "enabled onboard soundcard\n");
        }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
@@ -491,3 +493,20 @@ static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
                          pci_siemens_interrupt_controller);
+
+/*
+ * Regular PCI devices have 256 bytes, but AMD Family 10h Opteron ext config
+ * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
+ * access it.  Maybe we don't have a way to generate extended config space
+ * accesses.   So check it
+ */
+static void fam10h_pci_cfg_space_size(struct pci_dev *dev)
+{
+       dev->cfg_size = pci_cfg_space_size_ext(dev);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, fam10h_pci_cfg_space_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size);