AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
+ AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
/* ap->flags bits */
static void ahci_p5wdh_error_handler(struct ata_port *ap);
static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
static int ahci_port_resume(struct ata_port *ap);
+static void ahci_dev_config(struct ata_device *dev);
static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
u32 opts);
.check_altstatus = ahci_check_status,
.dev_select = ata_noop_dev_select,
+ .dev_config = ahci_dev_config,
+
.tf_read = ahci_tf_read,
.qc_defer = sata_pmp_qc_defer_cmd_switch,
/* board_ahci_sb600 */
{
AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
- AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
+ AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
.flags = AHCI_FLAG_COMMON,
.link_flags = AHCI_LFLAG_COMMON,
.pio_mask = 0x1f, /* pio0-4 */
{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
+ { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
+ { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
/* SiS */
{ PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
cap &= ~HOST_CAP_NCQ;
}
- if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
+ if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
dev_printk(KERN_INFO, &pdev->dev,
"controller can't do PMP, turning off CAP_PMP\n");
cap &= ~HOST_CAP_PMP;
VPRINTK("HOST_CTL 0x%x\n", tmp);
}
+static void ahci_dev_config(struct ata_device *dev)
+{
+ struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
+
+ if (hpriv->flags & AHCI_HFLAG_SECT255)
+ dev->max_sectors = 255;
+}
+
static unsigned int ahci_dev_classify(struct ata_port *ap)
{
void __iomem *port_mmio = ahci_port_base(ap);
if (rc)
return rc;
- rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
+ /* AHCI controllers often implement SFF compatible interface.
+ * Grab all PCI BARs just in case.
+ */
+ rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
if (rc == -EBUSY)
pcim_pin_device(pdev);
if (rc)