-/* -*- c-basic-offset: 8 -*-
+/*
+ * Driver for OHCI 1394 controllers
*
- * fw-ohci.c - Driver for OHCI 1394 boards
* Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
*
* This program is free software; you can redistribute it and/or modify
#include <linux/delay.h>
#include <linux/poll.h>
#include <linux/dma-mapping.h>
+#include <linux/mm.h>
#include <asm/uaccess.h>
#include <asm/semaphore.h>
#include "fw-transaction.h"
#include "fw-ohci.h"
-#define descriptor_output_more 0
-#define descriptor_output_last (1 << 12)
-#define descriptor_input_more (2 << 12)
-#define descriptor_input_last (3 << 12)
-#define descriptor_status (1 << 11)
-#define descriptor_key_immediate (2 << 8)
-#define descriptor_ping (1 << 7)
-#define descriptor_yy (1 << 6)
-#define descriptor_no_irq (0 << 4)
-#define descriptor_irq_error (1 << 4)
-#define descriptor_irq_always (3 << 4)
-#define descriptor_branch_always (3 << 2)
-#define descriptor_wait (3 << 0)
+#define DESCRIPTOR_OUTPUT_MORE 0
+#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
+#define DESCRIPTOR_INPUT_MORE (2 << 12)
+#define DESCRIPTOR_INPUT_LAST (3 << 12)
+#define DESCRIPTOR_STATUS (1 << 11)
+#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
+#define DESCRIPTOR_PING (1 << 7)
+#define DESCRIPTOR_YY (1 << 6)
+#define DESCRIPTOR_NO_IRQ (0 << 4)
+#define DESCRIPTOR_IRQ_ERROR (1 << 4)
+#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
+#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
+#define DESCRIPTOR_WAIT (3 << 0)
struct descriptor {
__le16 req_count;
__le32 reserved1;
} __attribute__((aligned(16)));
-#define control_set(regs) (regs)
-#define control_clear(regs) ((regs) + 4)
-#define command_ptr(regs) ((regs) + 12)
-#define context_match(regs) ((regs) + 16)
+#define CONTROL_SET(regs) (regs)
+#define CONTROL_CLEAR(regs) ((regs) + 4)
+#define COMMAND_PTR(regs) ((regs) + 12)
+#define CONTEXT_MATCH(regs) ((regs) + 16)
struct ar_buffer {
struct descriptor descriptor;
struct descriptor *d,
struct descriptor *last);
struct context {
- struct fw_ohci *ohci;
+ struct fw_ohci *ohci;
u32 regs;
-
+
struct descriptor *buffer;
dma_addr_t buffer_bus;
size_t buffer_size;
descriptor_callback_t callback;
- struct tasklet_struct tasklet;
-};
-
-
-
-struct at_context {
- struct fw_ohci *ohci;
- dma_addr_t descriptor_bus;
- dma_addr_t buffer_bus;
- struct fw_packet *current_packet;
-
- struct list_head list;
-
- struct {
- struct descriptor more;
- __le32 header[4];
- struct descriptor last;
- } d;
-
- u32 regs;
-
struct tasklet_struct tasklet;
};
-#define it_header_sy(v) ((v) << 0)
-#define it_header_tcode(v) ((v) << 4)
-#define it_header_channel(v) ((v) << 8)
-#define it_header_tag(v) ((v) << 14)
-#define it_header_speed(v) ((v) << 16)
-#define it_header_data_length(v) ((v) << 16)
+#define IT_HEADER_SY(v) ((v) << 0)
+#define IT_HEADER_TCODE(v) ((v) << 4)
+#define IT_HEADER_CHANNEL(v) ((v) << 8)
+#define IT_HEADER_TAG(v) ((v) << 14)
+#define IT_HEADER_SPEED(v) ((v) << 16)
+#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
struct iso_context {
struct fw_iso_context base;
int node_id;
int generation;
int request_generation;
+ u32 bus_seconds;
- /* Spinlock for accessing fw_ohci data. Never call out of
- * this driver with this lock held. */
+ /*
+ * Spinlock for accessing fw_ohci data. Never call out of
+ * this driver with this lock held.
+ */
spinlock_t lock;
u32 self_id_buffer[512];
struct ar_context ar_request_ctx;
struct ar_context ar_response_ctx;
- struct at_context at_request_ctx;
- struct at_context at_response_ctx;
+ struct context at_request_ctx;
+ struct context at_response_ctx;
u32 it_context_mask;
struct iso_context *it_context_list;
#define SELF_ID_BUF_SIZE 0x800
#define OHCI_TCODE_PHY_PACKET 0x0e
#define OHCI_VERSION_1_1 0x010010
+#define ISO_BUFFER_SIZE (64 * 1024)
+#define AT_BUFFER_SIZE 4096
static char ohci_driver_name[] = KBUILD_MODNAME;
return -ENOMEM;
}
- memset(&ab->descriptor, 0, sizeof ab->descriptor);
- ab->descriptor.control = cpu_to_le16(descriptor_input_more |
- descriptor_status |
- descriptor_branch_always);
+ memset(&ab->descriptor, 0, sizeof(ab->descriptor));
+ ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
+ DESCRIPTOR_STATUS |
+ DESCRIPTOR_BRANCH_ALWAYS);
offset = offsetof(struct ar_buffer, data);
ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
- ctx->last_buffer->descriptor.branch_address = ab_bus | 1;
+ ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
ctx->last_buffer->next = ab;
ctx->last_buffer = ab;
- reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
+ reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
flush_writes(ctx->ohci);
return 0;
p.timestamp = status & 0xffff;
p.generation = ohci->request_generation;
- /* The OHCI bus reset handler synthesizes a phy packet with
+ /*
+ * The OHCI bus reset handler synthesizes a phy packet with
* the new generation number when a bus reset happens (see
* section 8.4.2.3). This helps us determine when a request
* was received and make sure we send the response in the same
* generation. We only need this for requests; for responses
* we use the unique tlabel for finding the matching
- * request. */
+ * request.
+ */
if (p.ack + 16 == 0x09)
ohci->request_generation = (buffer[2] >> 16) & 0xff;
if (d->res_count == 0) {
size_t size, rest, offset;
- /* This descriptor is finished and we may have a
+ /*
+ * This descriptor is finished and we may have a
* packet split across this and the next buffer. We
- * reuse the page for reassembling the split packet. */
+ * reuse the page for reassembling the split packet.
+ */
offset = offsetof(struct ar_buffer, data);
dma_unmap_single(ohci->card.device,
ctx->current_buffer = ab.next;
ctx->pointer = ctx->current_buffer->data;
- reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address);
- reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN);
- flush_writes(ctx->ohci);
-
return 0;
}
-
+
+static void ar_context_run(struct ar_context *ctx)
+{
+ struct ar_buffer *ab = ctx->current_buffer;
+ dma_addr_t ab_bus;
+ size_t offset;
+
+ offset = offsetof(struct ar_buffer, data);
+ ab_bus = ab->descriptor.data_address - offset;
+
+ reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
+ reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
+ flush_writes(ctx->ohci);
+}
+
static void context_tasklet(unsigned long data)
{
struct context *ctx = (struct context *) data;
while (last->branch_address != 0) {
address = le32_to_cpu(last->branch_address);
z = address & 0xf;
- d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
+ d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
last = (z == 2) ? d : d + z - 1;
if (!ctx->callback(ctx, d, last))
ctx->tail_descriptor = ctx->buffer;
ctx->tail_descriptor_last = ctx->buffer;
- /* We put a dummy descriptor in the buffer that has a NULL
+ /*
+ * We put a dummy descriptor in the buffer that has a NULL
* branch address and looks like it's been sent. That way we
* have a descriptor to append DMA programs to. Also, the
* ring buffer invariant is that it always has at least one
- * element so that head == tail means buffer full. */
+ * element so that head == tail means buffer full.
+ */
- memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
- ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
+ memset(ctx->head_descriptor, 0, sizeof(*ctx->head_descriptor));
+ ctx->head_descriptor->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
ctx->head_descriptor++;
d = ctx->head_descriptor;
tail = ctx->tail_descriptor;
- end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor);
+ end = ctx->buffer + ctx->buffer_size / sizeof(*d);
if (d + z <= tail) {
goto has_space;
return NULL;
has_space:
- memset(d, 0, z * sizeof *d);
- *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
+ memset(d, 0, z * sizeof(*d));
+ *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
return d;
}
{
struct fw_ohci *ohci = ctx->ohci;
- reg_write(ohci, command_ptr(ctx->regs),
+ reg_write(ohci, COMMAND_PTR(ctx->regs),
le32_to_cpu(ctx->tail_descriptor_last->branch_address));
- reg_write(ohci, control_clear(ctx->regs), ~0);
- reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | extra);
+ reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
+ reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
flush_writes(ohci);
}
{
dma_addr_t d_bus;
- d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
+ d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof(*d);
ctx->head_descriptor = d + z + extra;
ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
ctx->buffer_size, DMA_TO_DEVICE);
- reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
+ reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
flush_writes(ctx->ohci);
}
u32 reg;
int i;
- reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
+ reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
flush_writes(ctx->ohci);
for (i = 0; i < 10; i++) {
- reg = reg_read(ctx->ohci, control_set(ctx->regs));
+ reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
if ((reg & CONTEXT_ACTIVE) == 0)
break;
}
}
-static void
-do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list)
-{
- struct fw_packet *p, *next;
-
- list_for_each_entry_safe(p, next, list, link)
- p->callback(p, &ohci->card, p->ack);
-}
-
-static void
-complete_transmission(struct fw_packet *packet,
- int ack, struct list_head *list)
-{
- list_move_tail(&packet->link, list);
- packet->ack = ack;
-}
+struct driver_data {
+ struct fw_packet *packet;
+};
-/* This function prepares the first packet in the context queue for
- * transmission. Must always be called with the ochi->lock held to
- * ensure proper generation handling and locking around packet queue
- * manipulation. */
-static void
-at_context_setup_packet(struct at_context *ctx, struct list_head *list)
+/*
+ * This function apppends a packet to the DMA queue for transmission.
+ * Must always be called with the ochi->lock held to ensure proper
+ * generation handling and locking around packet queue manipulation.
+ */
+static int
+at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
{
- struct fw_packet *packet;
struct fw_ohci *ohci = ctx->ohci;
+ dma_addr_t d_bus, payload_bus;
+ struct driver_data *driver_data;
+ struct descriptor *d, *last;
+ __le32 *header;
int z, tcode;
+ u32 reg;
- packet = fw_packet(ctx->list.next);
-
- memset(&ctx->d, 0, sizeof ctx->d);
- if (packet->payload_length > 0) {
- packet->payload_bus = dma_map_single(ohci->card.device,
- packet->payload,
- packet->payload_length,
- DMA_TO_DEVICE);
- if (dma_mapping_error(packet->payload_bus)) {
- complete_transmission(packet, RCODE_SEND_ERROR, list);
- return;
- }
-
- ctx->d.more.control =
- cpu_to_le16(descriptor_output_more |
- descriptor_key_immediate);
- ctx->d.more.req_count = cpu_to_le16(packet->header_length);
- ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
- ctx->d.last.control =
- cpu_to_le16(descriptor_output_last |
- descriptor_irq_always |
- descriptor_branch_always);
- ctx->d.last.req_count = cpu_to_le16(packet->payload_length);
- ctx->d.last.data_address = cpu_to_le32(packet->payload_bus);
- z = 3;
- } else {
- ctx->d.more.control =
- cpu_to_le16(descriptor_output_last |
- descriptor_key_immediate |
- descriptor_irq_always |
- descriptor_branch_always);
- ctx->d.more.req_count = cpu_to_le16(packet->header_length);
- ctx->d.more.res_count = cpu_to_le16(packet->timestamp);
- z = 2;
+ d = context_get_descriptors(ctx, 4, &d_bus);
+ if (d == NULL) {
+ packet->ack = RCODE_SEND_ERROR;
+ return -1;
}
- /* The DMA format for asyncronous link packets is different
+ d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
+ d[0].res_count = cpu_to_le16(packet->timestamp);
+
+ /*
+ * The DMA format for asyncronous link packets is different
* from the IEEE1394 layout, so shift the fields around
* accordingly. If header_length is 8, it's a PHY packet, to
- * which we need to prepend an extra quadlet. */
+ * which we need to prepend an extra quadlet.
+ */
+
+ header = (__le32 *) &d[1];
if (packet->header_length > 8) {
- ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
- (packet->speed << 16));
- ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
- (packet->header[0] & 0xffff0000));
- ctx->d.header[2] = cpu_to_le32(packet->header[2]);
+ header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
+ (packet->speed << 16));
+ header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
+ (packet->header[0] & 0xffff0000));
+ header[2] = cpu_to_le32(packet->header[2]);
tcode = (packet->header[0] >> 4) & 0x0f;
if (TCODE_IS_BLOCK_PACKET(tcode))
- ctx->d.header[3] = cpu_to_le32(packet->header[3]);
+ header[3] = cpu_to_le32(packet->header[3]);
else
- ctx->d.header[3] = packet->header[3];
+ header[3] = (__force __le32) packet->header[3];
+
+ d[0].req_count = cpu_to_le16(packet->header_length);
} else {
- ctx->d.header[0] =
- cpu_to_le32((OHCI1394_phy_tcode << 4) |
- (packet->speed << 16));
- ctx->d.header[1] = cpu_to_le32(packet->header[0]);
- ctx->d.header[2] = cpu_to_le32(packet->header[1]);
- ctx->d.more.req_count = cpu_to_le16(12);
+ header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
+ (packet->speed << 16));
+ header[1] = cpu_to_le32(packet->header[0]);
+ header[2] = cpu_to_le32(packet->header[1]);
+ d[0].req_count = cpu_to_le16(12);
}
- /* FIXME: Document how the locking works. */
- if (ohci->generation == packet->generation) {
- reg_write(ctx->ohci, command_ptr(ctx->regs),
- ctx->descriptor_bus | z);
- reg_write(ctx->ohci, control_set(ctx->regs),
- CONTEXT_RUN | CONTEXT_WAKE);
- ctx->current_packet = packet;
+ driver_data = (struct driver_data *) &d[3];
+ driver_data->packet = packet;
+ packet->driver_data = driver_data;
+
+ if (packet->payload_length > 0) {
+ payload_bus =
+ dma_map_single(ohci->card.device, packet->payload,
+ packet->payload_length, DMA_TO_DEVICE);
+ if (dma_mapping_error(payload_bus)) {
+ packet->ack = RCODE_SEND_ERROR;
+ return -1;
+ }
+
+ d[2].req_count = cpu_to_le16(packet->payload_length);
+ d[2].data_address = cpu_to_le32(payload_bus);
+ last = &d[2];
+ z = 3;
} else {
- /* We dont return error codes from this function; all
- * transmission errors are reported through the
- * callback. */
- complete_transmission(packet, RCODE_GENERATION, list);
+ last = &d[0];
+ z = 2;
}
-}
-static void at_context_stop(struct at_context *ctx)
-{
- u32 reg;
+ last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
+ DESCRIPTOR_IRQ_ALWAYS |
+ DESCRIPTOR_BRANCH_ALWAYS);
+
+ /* FIXME: Document how the locking works. */
+ if (ohci->generation != packet->generation) {
+ packet->ack = RCODE_GENERATION;
+ return -1;
+ }
+
+ context_append(ctx, d, z, 4 - z);
- reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
+ /* If the context isn't already running, start it up. */
+ reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
+ if ((reg & CONTEXT_RUN) == 0)
+ context_run(ctx, 0);
- reg = reg_read(ctx->ohci, control_set(ctx->regs));
- if (reg & CONTEXT_ACTIVE)
- fw_notify("Tried to stop context, but it is still active "
- "(0x%08x).\n", reg);
+ return 0;
}
-static void at_context_tasklet(unsigned long data)
+static int handle_at_packet(struct context *context,
+ struct descriptor *d,
+ struct descriptor *last)
{
- struct at_context *ctx = (struct at_context *)data;
- struct fw_ohci *ohci = ctx->ohci;
+ struct driver_data *driver_data;
struct fw_packet *packet;
- LIST_HEAD(list);
- unsigned long flags;
+ struct fw_ohci *ohci = context->ohci;
+ dma_addr_t payload_bus;
int evt;
- spin_lock_irqsave(&ohci->lock, flags);
-
- packet = fw_packet(ctx->list.next);
-
- at_context_stop(ctx);
+ if (last->transfer_status == 0)
+ /* This descriptor isn't done yet, stop iteration. */
+ return 0;
- /* If the head of the list isn't the packet that just got
- * transmitted, the packet got cancelled before we finished
- * transmitting it. */
- if (ctx->current_packet != packet)
- goto skip_to_next;
+ driver_data = (struct driver_data *) &d[3];
+ packet = driver_data->packet;
+ if (packet == NULL)
+ /* This packet was cancelled, just continue. */
+ return 1;
- if (packet->payload_length > 0) {
- dma_unmap_single(ohci->card.device, packet->payload_bus,
+ payload_bus = le32_to_cpu(last->data_address);
+ if (payload_bus != 0)
+ dma_unmap_single(ohci->card.device, payload_bus,
packet->payload_length, DMA_TO_DEVICE);
- evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f;
- packet->timestamp = le16_to_cpu(ctx->d.last.res_count);
- }
- else {
- evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f;
- packet->timestamp = le16_to_cpu(ctx->d.more.res_count);
- }
- if (evt < 16) {
- switch (evt) {
- case OHCI1394_evt_timeout:
- /* Async response transmit timed out. */
- complete_transmission(packet, RCODE_CANCELLED, &list);
- break;
+ evt = le16_to_cpu(last->transfer_status) & 0x1f;
+ packet->timestamp = le16_to_cpu(last->res_count);
- case OHCI1394_evt_flushed:
- /* The packet was flushed should give same
- * error as when we try to use a stale
- * generation count. */
- complete_transmission(packet,
- RCODE_GENERATION, &list);
- break;
-
- case OHCI1394_evt_missing_ack:
- /* Using a valid (current) generation count,
- * but the node is not on the bus or not
- * sending acks. */
- complete_transmission(packet, RCODE_NO_ACK, &list);
- break;
-
- default:
- complete_transmission(packet, RCODE_SEND_ERROR, &list);
- break;
- }
- } else
- complete_transmission(packet, evt - 16, &list);
-
- skip_to_next:
- /* If more packets are queued, set up the next one. */
- if (!list_empty(&ctx->list))
- at_context_setup_packet(ctx, &list);
-
- spin_unlock_irqrestore(&ohci->lock, flags);
+ switch (evt) {
+ case OHCI1394_evt_timeout:
+ /* Async response transmit timed out. */
+ packet->ack = RCODE_CANCELLED;
+ break;
- do_packet_callbacks(ohci, &list);
-}
+ case OHCI1394_evt_flushed:
+ /*
+ * The packet was flushed should give same error as
+ * when we try to use a stale generation count.
+ */
+ packet->ack = RCODE_GENERATION;
+ break;
-static int
-at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 regs)
-{
- INIT_LIST_HEAD(&ctx->list);
+ case OHCI1394_evt_missing_ack:
+ /*
+ * Using a valid (current) generation count, but the
+ * node is not on the bus or not sending acks.
+ */
+ packet->ack = RCODE_NO_ACK;
+ break;
- ctx->descriptor_bus =
- dma_map_single(ohci->card.device, &ctx->d,
- sizeof ctx->d, DMA_TO_DEVICE);
- if (dma_mapping_error(ctx->descriptor_bus))
- return -ENOMEM;
+ case ACK_COMPLETE + 0x10:
+ case ACK_PENDING + 0x10:
+ case ACK_BUSY_X + 0x10:
+ case ACK_BUSY_A + 0x10:
+ case ACK_BUSY_B + 0x10:
+ case ACK_DATA_ERROR + 0x10:
+ case ACK_TYPE_ERROR + 0x10:
+ packet->ack = evt - 0x10;
+ break;
- ctx->regs = regs;
- ctx->ohci = ohci;
+ default:
+ packet->ack = RCODE_SEND_ERROR;
+ break;
+ }
- tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx);
+ packet->callback(packet, &ohci->card, packet->ack);
- return 0;
+ return 1;
}
-#define header_get_destination(q) (((q) >> 16) & 0xffff)
-#define header_get_tcode(q) (((q) >> 4) & 0x0f)
-#define header_get_offset_high(q) (((q) >> 0) & 0xffff)
-#define header_get_data_length(q) (((q) >> 16) & 0xffff)
-#define header_get_extended_tcode(q) (((q) >> 0) & 0xffff)
+#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
+#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
+#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
+#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
+#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
static void
handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
struct fw_packet response;
int tcode, length, i;
- tcode = header_get_tcode(packet->header[0]);
+ tcode = HEADER_GET_TCODE(packet->header[0]);
if (TCODE_IS_BLOCK_PACKET(tcode))
- length = header_get_data_length(packet->header[3]);
+ length = HEADER_GET_DATA_LENGTH(packet->header[3]);
else
length = 4;
__be32 *payload, lock_old;
u32 lock_arg, lock_data;
- tcode = header_get_tcode(packet->header[0]);
- length = header_get_data_length(packet->header[3]);
+ tcode = HEADER_GET_TCODE(packet->header[0]);
+ length = HEADER_GET_DATA_LENGTH(packet->header[3]);
payload = packet->payload;
- ext_tcode = header_get_extended_tcode(packet->header[3]);
+ ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
if (tcode == TCODE_LOCK_REQUEST &&
ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
fw_notify("swap not done yet\n");
fw_fill_response(&response, packet->header,
- RCODE_COMPLETE, &lock_old, sizeof lock_old);
+ RCODE_COMPLETE, &lock_old, sizeof(lock_old));
out:
fw_core_handle_response(&ohci->card, &response);
}
static void
-handle_local_request(struct at_context *ctx, struct fw_packet *packet)
+handle_local_request(struct context *ctx, struct fw_packet *packet)
{
u64 offset;
u32 csr;
- packet->ack = ACK_PENDING;
- packet->callback(packet, &ctx->ohci->card, packet->ack);
+ if (ctx == &ctx->ohci->at_request_ctx) {
+ packet->ack = ACK_PENDING;
+ packet->callback(packet, &ctx->ohci->card, packet->ack);
+ }
offset =
((unsigned long long)
- header_get_offset_high(packet->header[1]) << 32) |
+ HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
packet->header[2];
csr = offset - CSR_REGISTER_BASE;
fw_core_handle_response(&ctx->ohci->card, packet);
break;
}
+
+ if (ctx == &ctx->ohci->at_response_ctx) {
+ packet->ack = ACK_COMPLETE;
+ packet->callback(packet, &ctx->ohci->card, packet->ack);
+ }
}
static void
-at_context_transmit(struct at_context *ctx, struct fw_packet *packet)
+at_context_transmit(struct context *ctx, struct fw_packet *packet)
{
- LIST_HEAD(list);
unsigned long flags;
+ int retval;
spin_lock_irqsave(&ctx->ohci->lock, flags);
- if (header_get_destination(packet->header[0]) == ctx->ohci->node_id &&
+ if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
ctx->ohci->generation == packet->generation) {
spin_unlock_irqrestore(&ctx->ohci->lock, flags);
handle_local_request(ctx, packet);
return;
}
- list_add_tail(&packet->link, &ctx->list);
- if (ctx->list.next == &packet->link)
- at_context_setup_packet(ctx, &list);
-
+ retval = at_context_queue_packet(ctx, packet);
spin_unlock_irqrestore(&ctx->ohci->lock, flags);
- do_packet_callbacks(ctx->ohci, &list);
+ if (retval < 0)
+ packet->callback(packet, &ctx->ohci->card, packet->ack);
+
}
static void bus_reset_tasklet(unsigned long data)
}
ohci->node_id = reg & 0xffff;
- /* The count in the SelfIDCount register is the number of
+ /*
+ * The count in the SelfIDCount register is the number of
* bytes in the self ID receive buffer. Since we also receive
* the inverted quadlets and a header quadlet, we shift one
- * bit extra to get the actual number of self IDs. */
+ * bit extra to get the actual number of self IDs.
+ */
self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
}
- /* Check the consistency of the self IDs we just read. The
+ /*
+ * Check the consistency of the self IDs we just read. The
* problem we face is that a new bus reset can start while we
* read out the self IDs from the DMA buffer. If this happens,
* the DMA buffer will be overwritten with new self IDs and we
* self IDs in the buffer before reading them out and compare
* it to the current generation after reading them out. If
* the two generations match we know we have a consistent set
- * of self IDs. */
+ * of self IDs.
+ */
new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
if (new_generation != generation) {
spin_lock_irqsave(&ohci->lock, flags);
ohci->generation = generation;
- at_context_stop(&ohci->at_request_ctx);
- at_context_stop(&ohci->at_response_ctx);
+ context_stop(&ohci->at_request_ctx);
+ context_stop(&ohci->at_response_ctx);
reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
- /* This next bit is unrelated to the AT context stuff but we
+ /*
+ * This next bit is unrelated to the AT context stuff but we
* have to do it under the spinlock also. If a new config rom
* was set up before this reset, the old one is now no longer
* in use and we can free it. Update the config rom pointers
* to point to the current config rom and clear the
- * next_config_rom pointer so a new udpate can take place. */
+ * next_config_rom pointer so a new udpate can take place.
+ */
if (ohci->next_config_rom != NULL) {
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
ohci->config_rom_bus = ohci->next_config_rom_bus;
ohci->next_config_rom = NULL;
- /* Restore config_rom image and manually update
+ /*
+ * Restore config_rom image and manually update
* config_rom registers. Writing the header quadlet
* will indicate that the config rom is ready, so we
- * do that last. */
+ * do that last.
+ */
reg_write(ohci, OHCI1394_BusOptions,
be32_to_cpu(ohci->config_rom[2]));
ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
static irqreturn_t irq_handler(int irq, void *data)
{
struct fw_ohci *ohci = data;
- u32 event, iso_event;
+ u32 event, iso_event, cycle_time;
int i;
event = reg_read(ohci, OHCI1394_IntEventClear);
iso_event &= ~(1 << i);
}
+ if (event & OHCI1394_cycle64Seconds) {
+ cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
+ if ((cycle_time & 0x80000000) == 0)
+ ohci->bus_seconds++;
+ }
+
return IRQ_HANDLED;
}
+static int software_reset(struct fw_ohci *ohci)
+{
+ int i;
+
+ reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
+
+ for (i = 0; i < OHCI_LOOP_COUNT; i++) {
+ if ((reg_read(ohci, OHCI1394_HCControlSet) &
+ OHCI1394_HCControl_softReset) == 0)
+ return 0;
+ msleep(1);
+ }
+
+ return -EBUSY;
+}
+
static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
{
struct fw_ohci *ohci = fw_ohci(card);
struct pci_dev *dev = to_pci_dev(card->device);
- /* When the link is not yet enabled, the atomic config rom
+ if (software_reset(ohci)) {
+ fw_error("Failed to reset ohci card.\n");
+ return -EBUSY;
+ }
+
+ /*
+ * Now enable LPS, which we need in order to start accessing
+ * most of the registers. In fact, on some cards (ALI M5251),
+ * accessing registers in the SClk domain without LPS enabled
+ * will lock up the machine. Wait 50msec to make sure we have
+ * full link enabled.
+ */
+ reg_write(ohci, OHCI1394_HCControlSet,
+ OHCI1394_HCControl_LPS |
+ OHCI1394_HCControl_postedWriteEnable);
+ flush_writes(ohci);
+ msleep(50);
+
+ reg_write(ohci, OHCI1394_HCControlClear,
+ OHCI1394_HCControl_noByteSwapData);
+
+ reg_write(ohci, OHCI1394_LinkControlSet,
+ OHCI1394_LinkControl_rcvSelfID |
+ OHCI1394_LinkControl_cycleTimerEnable |
+ OHCI1394_LinkControl_cycleMaster);
+
+ reg_write(ohci, OHCI1394_ATRetries,
+ OHCI1394_MAX_AT_REQ_RETRIES |
+ (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
+ (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
+
+ ar_context_run(&ohci->ar_request_ctx);
+ ar_context_run(&ohci->ar_response_ctx);
+
+ reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
+ reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
+ reg_write(ohci, OHCI1394_IntEventClear, ~0);
+ reg_write(ohci, OHCI1394_IntMaskClear, ~0);
+ reg_write(ohci, OHCI1394_IntMaskSet,
+ OHCI1394_selfIDComplete |
+ OHCI1394_RQPkt | OHCI1394_RSPkt |
+ OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
+ OHCI1394_isochRx | OHCI1394_isochTx |
+ OHCI1394_masterIntEnable |
+ OHCI1394_cycle64Seconds);
+
+ /* Activate link_on bit and contender bit in our self ID packets.*/
+ if (ohci_update_phy_reg(card, 4, 0,
+ PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
+ return -EIO;
+
+ /*
+ * When the link is not yet enabled, the atomic config rom
* update mechanism described below in ohci_set_config_rom()
* is not active. We have to update ConfigRomHeader and
* BusOptions manually, and the write to ConfigROMmap takes
reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
if (request_irq(dev->irq, irq_handler,
- SA_SHIRQ, ohci_driver_name, ohci)) {
+ IRQF_SHARED, ohci_driver_name, ohci)) {
fw_error("Failed to allocate shared interrupt %d.\n",
dev->irq);
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
OHCI1394_HCControl_BIBimageValid);
flush_writes(ohci);
- /* We are ready to go, initiate bus reset to finish the
- * initialization. */
+ /*
+ * We are ready to go, initiate bus reset to finish the
+ * initialization.
+ */
fw_core_initiate_bus_reset(&ohci->card, 1);
ohci = fw_ohci(card);
- /* When the OHCI controller is enabled, the config rom update
+ /*
+ * When the OHCI controller is enabled, the config rom update
* mechanism is a bit tricky, but easy enough to use. See
* section 5.5.6 in the OHCI specification.
*
spin_unlock_irqrestore(&ohci->lock, flags);
- /* Now initiate a bus reset to have the changes take
+ /*
+ * Now initiate a bus reset to have the changes take
* effect. We clean up the old config rom memory and DMA
* mappings in the bus reset tasklet, since the OHCI
* controller could need to access it before the bus reset
- * takes effect. */
+ * takes effect.
+ */
if (retval == 0)
fw_core_initiate_bus_reset(&ohci->card, 1);
static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
{
struct fw_ohci *ohci = fw_ohci(card);
- LIST_HEAD(list);
- unsigned long flags;
+ struct context *ctx = &ohci->at_request_ctx;
+ struct driver_data *driver_data = packet->driver_data;
+ int retval = -ENOENT;
- spin_lock_irqsave(&ohci->lock, flags);
+ tasklet_disable(&ctx->tasklet);
- if (packet->ack == 0) {
- fw_notify("cancelling packet %p (header[0]=%08x)\n",
- packet, packet->header[0]);
+ if (packet->ack != 0)
+ goto out;
- complete_transmission(packet, RCODE_CANCELLED, &list);
- }
+ driver_data->packet = NULL;
+ packet->ack = RCODE_CANCELLED;
+ packet->callback(packet, &ohci->card, packet->ack);
+ retval = 0;
- spin_unlock_irqrestore(&ohci->lock, flags);
-
- do_packet_callbacks(ohci, &list);
+ out:
+ tasklet_enable(&ctx->tasklet);
- /* Return success if we actually cancelled something. */
- return list_empty(&list) ? -ENOENT : 0;
+ return retval;
}
static int
unsigned long flags;
int n, retval = 0;
- /* FIXME: Make sure this bitmask is cleared when we clear the busReset
- * interrupt bit. Clear physReqResourceAllBuses on bus reset. */
+ /*
+ * FIXME: Make sure this bitmask is cleared when we clear the busReset
+ * interrupt bit. Clear physReqResourceAllBuses on bus reset.
+ */
spin_lock_irqsave(&ohci->lock, flags);
goto out;
}
- /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
- * enabled for _all_ nodes on remote buses. */
+ /*
+ * Note, if the node ID contains a non-local bus ID, physical DMA is
+ * enabled for _all_ nodes on remote buses.
+ */
n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
if (n < 32)
spin_unlock_irqrestore(&ohci->lock, flags);
return retval;
}
-
-static int handle_ir_bufferfill_packet(struct context *context,
- struct descriptor *d,
- struct descriptor *last)
+
+static u64
+ohci_get_bus_time(struct fw_card *card)
{
- struct iso_context *ctx =
- container_of(context, struct iso_context, context);
+ struct fw_ohci *ohci = fw_ohci(card);
+ u32 cycle_time;
+ u64 bus_time;
- if (d->res_count > 0)
- return 0;
+ cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
+ bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
- if (le16_to_cpu(last->control) & descriptor_irq_always)
- ctx->base.callback(&ctx->base,
- le16_to_cpu(last->res_count),
- 0, NULL, ctx->base.callback_data);
-
- return 1;
+ return bus_time;
}
static int handle_ir_dualbuffer_packet(struct context *context,
struct iso_context *ctx =
container_of(context, struct iso_context, context);
struct db_descriptor *db = (struct db_descriptor *) d;
+ __le32 *ir_header;
size_t header_length;
+ void *p, *end;
+ int i;
if (db->first_res_count > 0 && db->second_res_count > 0)
/* This descriptor isn't done yet, stop iteration. */
return 0;
- header_length = db->first_req_count - db->first_res_count;
- if (ctx->header_length + header_length <= PAGE_SIZE)
- memcpy(ctx->header + ctx->header_length, db + 1, header_length);
- ctx->header_length += header_length;
+ header_length = le16_to_cpu(db->first_req_count) -
+ le16_to_cpu(db->first_res_count);
+
+ i = ctx->header_length;
+ p = db + 1;
+ end = p + header_length;
+ while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
+ /*
+ * The iso header is byteswapped to little endian by
+ * the controller, but the remaining header quadlets
+ * are big endian. We want to present all the headers
+ * as big endian, so we have to swap the first
+ * quadlet.
+ */
+ *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
+ memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
+ i += ctx->base.header_size;
+ p += ctx->base.header_size + 4;
+ }
- if (le16_to_cpu(db->control) & descriptor_irq_always) {
- ctx->base.callback(&ctx->base, 0,
+ ctx->header_length = i;
+
+ if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
+ ir_header = (__le32 *) (db + 1);
+ ctx->base.callback(&ctx->base,
+ le32_to_cpu(ir_header[0]) & 0xffff,
ctx->header_length, ctx->header,
ctx->base.callback_data);
ctx->header_length = 0;
return 1;
}
-#define ISO_BUFFER_SIZE (64 * 1024)
-
static int handle_it_packet(struct context *context,
struct descriptor *d,
struct descriptor *last)
{
struct iso_context *ctx =
container_of(context, struct iso_context, context);
-
+
if (last->transfer_status == 0)
/* This descriptor isn't done yet, stop iteration. */
return 0;
- if (le16_to_cpu(last->control) & descriptor_irq_always)
+ if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
0, NULL, ctx->base.callback_data);
list = ohci->it_context_list;
callback = handle_it_packet;
} else {
- mask = &ohci->ir_context_mask;
- list = ohci->ir_context_list;
- if (header_size > 0)
- callback = handle_ir_dualbuffer_packet;
- else
- callback = handle_ir_bufferfill_packet;
+ mask = &ohci->ir_context_mask;
+ list = ohci->ir_context_list;
+ callback = handle_ir_dualbuffer_packet;
}
+ /* FIXME: We need a fallback for pre 1.1 OHCI. */
if (callback == handle_ir_dualbuffer_packet &&
ohci->version < OHCI_VERSION_1_1)
return ERR_PTR(-EINVAL);
if (index < 0)
return ERR_PTR(-EBUSY);
- if (type == FW_ISO_CONTEXT_TRANSMIT)
- regs = OHCI1394_IsoXmitContextBase(index);
- else
- regs = OHCI1394_IsoRcvContextBase(index);
-
+ if (type == FW_ISO_CONTEXT_TRANSMIT)
+ regs = OHCI1394_IsoXmitContextBase(index);
+ else
+ regs = OHCI1394_IsoRcvContextBase(index);
+
ctx = &list[index];
- memset(ctx, 0, sizeof *ctx);
+ memset(ctx, 0, sizeof(*ctx));
ctx->header_length = 0;
ctx->header = (void *) __get_free_page(GFP_KERNEL);
if (ctx->header == NULL)
return ERR_PTR(retval);
}
-static int ohci_start_iso(struct fw_iso_context *base, s32 cycle)
+static int ohci_start_iso(struct fw_iso_context *base,
+ s32 cycle, u32 sync, u32 tags)
{
- struct iso_context *ctx = container_of(base, struct iso_context, base);
+ struct iso_context *ctx = container_of(base, struct iso_context, base);
struct fw_ohci *ohci = ctx->context.ohci;
- u32 cycle_match = 0, mode;
+ u32 control, match;
int index;
if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
index = ctx - ohci->it_context_list;
- if (cycle > 0)
- cycle_match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
+ match = 0;
+ if (cycle >= 0)
+ match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
(cycle & 0x7fff) << 16;
reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
- context_run(&ctx->context, cycle_match);
+ context_run(&ctx->context, match);
} else {
index = ctx - ohci->ir_context_list;
+ control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER;
+ match = (tags << 28) | (sync << 8) | ctx->base.channel;
+ if (cycle >= 0) {
+ match |= (cycle & 0x07fff) << 12;
+ control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
+ }
- if (ctx->base.header_size > 0)
- mode = IR_CONTEXT_DUAL_BUFFER_MODE;
- else
- mode = IR_CONTEXT_BUFFER_FILL;
reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
- reg_write(ohci, context_match(ctx->context.regs),
- 0xf0000000 | ctx->base.channel);
- context_run(&ctx->context, mode);
+ reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
+ context_run(&ctx->context, control);
}
return 0;
static int ohci_stop_iso(struct fw_iso_context *base)
{
struct fw_ohci *ohci = fw_ohci(base->card);
- struct iso_context *ctx = container_of(base, struct iso_context, base);
+ struct iso_context *ctx = container_of(base, struct iso_context, base);
int index;
if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
static void ohci_free_iso_context(struct fw_iso_context *base)
{
struct fw_ohci *ohci = fw_ohci(base->card);
- struct iso_context *ctx = container_of(base, struct iso_context, base);
+ struct iso_context *ctx = container_of(base, struct iso_context, base);
unsigned long flags;
int index;
struct fw_iso_buffer *buffer,
unsigned long payload)
{
- struct iso_context *ctx = container_of(base, struct iso_context, base);
+ struct iso_context *ctx = container_of(base, struct iso_context, base);
struct descriptor *d, *last, *pd;
struct fw_iso_packet *p;
__le32 *header;
u32 payload_index, payload_end_index, next_page_index;
int page, end_page, i, length, offset;
- /* FIXME: Cycle lost behavior should be configurable: lose
- * packet, retransmit or terminate.. */
+ /*
+ * FIXME: Cycle lost behavior should be configurable: lose
+ * packet, retransmit or terminate..
+ */
p = packet;
payload_index = payload;
z += payload_z;
/* Get header size in number of descriptors. */
- header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
+ header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
if (d == NULL)
return -ENOMEM;
if (!p->skip) {
- d[0].control = cpu_to_le16(descriptor_key_immediate);
+ d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
d[0].req_count = cpu_to_le16(8);
header = (__le32 *) &d[1];
- header[0] = cpu_to_le32(it_header_sy(p->sy) |
- it_header_tag(p->tag) |
- it_header_tcode(TCODE_STREAM_DATA) |
- it_header_channel(ctx->base.channel) |
- it_header_speed(ctx->base.speed));
+ header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
+ IT_HEADER_TAG(p->tag) |
+ IT_HEADER_TCODE(TCODE_STREAM_DATA) |
+ IT_HEADER_CHANNEL(ctx->base.channel) |
+ IT_HEADER_SPEED(ctx->base.speed));
header[1] =
- cpu_to_le32(it_header_data_length(p->header_length +
+ cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
p->payload_length));
}
if (p->header_length > 0) {
d[2].req_count = cpu_to_le16(p->header_length);
- d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
+ d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
memcpy(&d[z], p->header, p->header_length);
}
}
if (p->interrupt)
- irq = descriptor_irq_always;
+ irq = DESCRIPTOR_IRQ_ALWAYS;
else
- irq = descriptor_no_irq;
+ irq = DESCRIPTOR_NO_IRQ;
last = z == 2 ? d : d + z - 1;
- last->control |= cpu_to_le16(descriptor_output_last |
- descriptor_status |
- descriptor_branch_always |
+ last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
+ DESCRIPTOR_STATUS |
+ DESCRIPTOR_BRANCH_ALWAYS |
irq);
context_append(&ctx->context, d, z, header_z);
struct fw_iso_packet *p;
dma_addr_t d_bus, page_bus;
u32 z, header_z, length, rest;
- int page, offset;
-
- /* FIXME: Cycle lost behavior should be configurable: lose
- * packet, retransmit or terminate.. */
+ int page, offset, packet_count, header_size;
+
+ /*
+ * FIXME: Cycle lost behavior should be configurable: lose
+ * packet, retransmit or terminate..
+ */
+
+ if (packet->skip) {
+ d = context_get_descriptors(&ctx->context, 2, &d_bus);
+ if (d == NULL)
+ return -ENOMEM;
+
+ db = (struct db_descriptor *) d;
+ db->control = cpu_to_le16(DESCRIPTOR_STATUS |
+ DESCRIPTOR_BRANCH_ALWAYS |
+ DESCRIPTOR_WAIT);
+ db->first_size = cpu_to_le16(ctx->base.header_size + 4);
+ context_append(&ctx->context, d, 2, 0);
+ }
p = packet;
z = 2;
+ /*
+ * The OHCI controller puts the status word in the header
+ * buffer too, so we need 4 extra bytes per packet.
+ */
+ packet_count = p->header_length / ctx->base.header_size;
+ header_size = packet_count * (ctx->base.header_size + 4);
+
/* Get header size in number of descriptors. */
- header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
+ header_z = DIV_ROUND_UP(header_size, sizeof(*d));
page = payload >> PAGE_SHIFT;
offset = payload & ~PAGE_MASK;
rest = p->payload_length;
/* FIXME: OHCI 1.0 doesn't support dual buffer receive */
- /* FIXME: handle descriptor_wait */
/* FIXME: make packet-per-buffer/dual-buffer a context option */
while (rest > 0) {
d = context_get_descriptors(&ctx->context,
return -ENOMEM;
db = (struct db_descriptor *) d;
- db->control = cpu_to_le16(descriptor_status |
- descriptor_branch_always);
- db->first_size = cpu_to_le16(ctx->base.header_size);
- db->first_req_count = cpu_to_le16(p->header_length);
+ db->control = cpu_to_le16(DESCRIPTOR_STATUS |
+ DESCRIPTOR_BRANCH_ALWAYS);
+ db->first_size = cpu_to_le16(ctx->base.header_size + 4);
+ db->first_req_count = cpu_to_le16(header_size);
db->first_res_count = db->first_req_count;
- db->first_buffer = cpu_to_le32(d_bus + sizeof *db);
-
+ db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
+
if (offset + rest < PAGE_SIZE)
length = rest;
else
db->second_buffer = cpu_to_le32(page_bus + offset);
if (p->interrupt && length == rest)
- db->control |= cpu_to_le16(descriptor_irq_always);
+ db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
context_append(&ctx->context, d, z, header_z);
offset = (offset + length) & ~PAGE_MASK;
return 0;
}
-static int
-ohci_queue_iso_receive_bufferfill(struct fw_iso_context *base,
- struct fw_iso_packet *packet,
- struct fw_iso_buffer *buffer,
- unsigned long payload)
-{
- struct iso_context *ctx = container_of(base, struct iso_context, base);
- struct descriptor *d = NULL;
- dma_addr_t d_bus, page_bus;
- u32 length, rest;
- int page, offset;
-
- page = payload >> PAGE_SHIFT;
- offset = payload & ~PAGE_MASK;
- rest = packet->payload_length;
-
- while (rest > 0) {
- d = context_get_descriptors(&ctx->context, 1, &d_bus);
- if (d == NULL)
- return -ENOMEM;
-
- d->control = cpu_to_le16(descriptor_input_more |
- descriptor_status |
- descriptor_branch_always);
-
- if (offset + rest < PAGE_SIZE)
- length = rest;
- else
- length = PAGE_SIZE - offset;
-
- page_bus = page_private(buffer->pages[page]);
- d->data_address = cpu_to_le32(page_bus + offset);
- d->req_count = cpu_to_le16(length);
- d->res_count = cpu_to_le16(length);
-
- if (packet->interrupt && length == rest)
- d->control |= cpu_to_le16(descriptor_irq_always);
-
- context_append(&ctx->context, d, 1, 0);
-
- offset = (offset + length) & ~PAGE_MASK;
- rest -= length;
- page++;
- }
-
- return 0;
-}
-
static int
ohci_queue_iso(struct fw_iso_context *base,
struct fw_iso_packet *packet,
if (base->type == FW_ISO_CONTEXT_TRANSMIT)
return ohci_queue_iso_transmit(base, packet, buffer, payload);
- else if (base->header_size == 0)
- return ohci_queue_iso_receive_bufferfill(base, packet,
- buffer, payload);
else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
return ohci_queue_iso_receive_dualbuffer(base, packet,
buffer, payload);
.send_response = ohci_send_response,
.cancel_packet = ohci_cancel_packet,
.enable_phys_dma = ohci_enable_phys_dma,
+ .get_bus_time = ohci_get_bus_time,
.allocate_iso_context = ohci_allocate_iso_context,
.free_iso_context = ohci_free_iso_context,
.stop_iso = ohci_stop_iso,
};
-static int software_reset(struct fw_ohci *ohci)
-{
- int i;
-
- reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
-
- for (i = 0; i < OHCI_LOOP_COUNT; i++) {
- if ((reg_read(ohci, OHCI1394_HCControlSet) &
- OHCI1394_HCControl_softReset) == 0)
- return 0;
- msleep(1);
- }
-
- return -EBUSY;
-}
-
-/* ---------- pci subsystem interface ---------- */
-
-enum {
- CLEANUP_SELF_ID,
- CLEANUP_REGISTERS,
- CLEANUP_IOMEM,
- CLEANUP_DISABLE,
- CLEANUP_PUT_CARD,
-};
-
-static int cleanup(struct fw_ohci *ohci, int stage, int code)
-{
- struct pci_dev *dev = to_pci_dev(ohci->card.device);
-
- switch (stage) {
- case CLEANUP_SELF_ID:
- dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
- ohci->self_id_cpu, ohci->self_id_bus);
- case CLEANUP_REGISTERS:
- kfree(ohci->it_context_list);
- kfree(ohci->ir_context_list);
- pci_iounmap(dev, ohci->registers);
- case CLEANUP_IOMEM:
- pci_release_region(dev, 0);
- case CLEANUP_DISABLE:
- pci_disable_device(dev);
- case CLEANUP_PUT_CARD:
- fw_card_put(&ohci->card);
- }
-
- return code;
-}
-
static int __devinit
pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct fw_ohci *ohci;
u32 bus_options, max_receive, link_speed;
u64 guid;
- int error_code;
+ int err;
size_t size;
- ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
+ ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
if (ohci == NULL) {
fw_error("Could not malloc fw_ohci data.\n");
return -ENOMEM;
fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
- if (pci_enable_device(dev)) {
+ err = pci_enable_device(dev);
+ if (err) {
fw_error("Failed to enable OHCI hardware.\n");
- return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
+ goto fail_put_card;
}
pci_set_master(dev);
tasklet_init(&ohci->bus_reset_tasklet,
bus_reset_tasklet, (unsigned long)ohci);
- if (pci_request_region(dev, 0, ohci_driver_name)) {
+ err = pci_request_region(dev, 0, ohci_driver_name);
+ if (err) {
fw_error("MMIO resource unavailable\n");
- return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
+ goto fail_disable;
}
ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
if (ohci->registers == NULL) {
fw_error("Failed to remap registers\n");
- return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
- }
-
- if (software_reset(ohci)) {
- fw_error("Failed to reset ohci card.\n");
- return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
+ err = -ENXIO;
+ goto fail_iomem;
}
- /* Now enable LPS, which we need in order to start accessing
- * most of the registers. In fact, on some cards (ALI M5251),
- * accessing registers in the SClk domain without LPS enabled
- * will lock up the machine. Wait 50msec to make sure we have
- * full link enabled. */
- reg_write(ohci, OHCI1394_HCControlSet,
- OHCI1394_HCControl_LPS |
- OHCI1394_HCControl_postedWriteEnable);
- flush_writes(ohci);
- msleep(50);
-
- reg_write(ohci, OHCI1394_HCControlClear,
- OHCI1394_HCControl_noByteSwapData);
-
- reg_write(ohci, OHCI1394_LinkControlSet,
- OHCI1394_LinkControl_rcvSelfID |
- OHCI1394_LinkControl_cycleTimerEnable |
- OHCI1394_LinkControl_cycleMaster);
-
ar_context_init(&ohci->ar_request_ctx, ohci,
OHCI1394_AsReqRcvContextControlSet);
ar_context_init(&ohci->ar_response_ctx, ohci,
OHCI1394_AsRspRcvContextControlSet);
- at_context_init(&ohci->at_request_ctx, ohci,
- OHCI1394_AsReqTrContextControlSet);
+ context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
+ OHCI1394_AsReqTrContextControlSet, handle_at_packet);
- at_context_init(&ohci->at_response_ctx, ohci,
- OHCI1394_AsRspTrContextControlSet);
-
- reg_write(ohci, OHCI1394_ATRetries,
- OHCI1394_MAX_AT_REQ_RETRIES |
- (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
- (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
+ context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
+ OHCI1394_AsRspTrContextControlSet, handle_at_packet);
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
fw_error("Out of memory for it/ir contexts.\n");
- return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
+ err = -ENOMEM;
+ goto fail_registers;
}
/* self-id dma buffer allocation */
GFP_KERNEL);
if (ohci->self_id_cpu == NULL) {
fw_error("Out of memory for self ID buffer.\n");
- return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
+ err = -ENOMEM;
+ goto fail_registers;
}
- reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
- reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
- reg_write(ohci, OHCI1394_IntEventClear, ~0);
- reg_write(ohci, OHCI1394_IntMaskClear, ~0);
- reg_write(ohci, OHCI1394_IntMaskSet,
- OHCI1394_selfIDComplete |
- OHCI1394_RQPkt | OHCI1394_RSPkt |
- OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
- OHCI1394_isochRx | OHCI1394_isochTx |
- OHCI1394_masterIntEnable);
-
bus_options = reg_read(ohci, OHCI1394_BusOptions);
max_receive = (bus_options >> 12) & 0xf;
link_speed = bus_options & 0x7;
guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
reg_read(ohci, OHCI1394_GUIDLo);
- error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
- if (error_code < 0)
- return cleanup(ohci, CLEANUP_SELF_ID, error_code);
+ err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
+ if (err < 0)
+ goto fail_self_id;
ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
return 0;
+
+ fail_self_id:
+ dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
+ ohci->self_id_cpu, ohci->self_id_bus);
+ fail_registers:
+ kfree(ohci->it_context_list);
+ kfree(ohci->ir_context_list);
+ pci_iounmap(dev, ohci->registers);
+ fail_iomem:
+ pci_release_region(dev, 0);
+ fail_disable:
+ pci_disable_device(dev);
+ fail_put_card:
+ fw_card_put(&ohci->card);
+
+ return err;
}
static void pci_remove(struct pci_dev *dev)
struct fw_ohci *ohci;
ohci = pci_get_drvdata(dev);
- reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable);
+ reg_write(ohci, OHCI1394_IntMaskClear, ~0);
+ flush_writes(ohci);
fw_core_remove_card(&ohci->card);
- /* FIXME: Fail all pending packets here, now that the upper
- * layers can't queue any more. */
+ /*
+ * FIXME: Fail all pending packets here, now that the upper
+ * layers can't queue any more.
+ */
software_reset(ohci);
free_irq(dev->irq, ohci);
- cleanup(ohci, CLEANUP_SELF_ID, 0);
+ dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
+ ohci->self_id_cpu, ohci->self_id_bus);
+ kfree(ohci->it_context_list);
+ kfree(ohci->ir_context_list);
+ pci_iounmap(dev, ohci->registers);
+ pci_release_region(dev, 0);
+ pci_disable_device(dev);
+ fw_card_put(&ohci->card);
fw_notify("Removed fw-ohci device.\n");
}
+#ifdef CONFIG_PM
+static int pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct fw_ohci *ohci = pci_get_drvdata(pdev);
+ int err;
+
+ software_reset(ohci);
+ free_irq(pdev->irq, ohci);
+ err = pci_save_state(pdev);
+ if (err) {
+ fw_error("pci_save_state failed with %d", err);
+ return err;
+ }
+ err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
+ if (err) {
+ fw_error("pci_set_power_state failed with %d", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static int pci_resume(struct pci_dev *pdev)
+{
+ struct fw_ohci *ohci = pci_get_drvdata(pdev);
+ int err;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+ err = pci_enable_device(pdev);
+ if (err) {
+ fw_error("pci_enable_device failed with %d", err);
+ return err;
+ }
+
+ return ohci_enable(&ohci->card, ohci->config_rom, CONFIG_ROM_SIZE);
+}
+#endif
+
static struct pci_device_id pci_table[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
{ }
.id_table = pci_table,
.probe = pci_probe,
.remove = pci_remove,
+#ifdef CONFIG_PM
+ .resume = pci_resume,
+ .suspend = pci_suspend,
+#endif
};
MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
MODULE_LICENSE("GPL");
+/* Provide a module alias so root-on-sbp2 initrds don't break. */
+#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
+MODULE_ALIAS("ohci1394");
+#endif
+
static int __init fw_ohci_init(void)
{
return pci_register_driver(&fw_ohci_pci_driver);
projects / linux-2.6-omap-h63xx.git / blobdiff