ide: add ide_pio_cycle_time() helper (take 2)

[linux-2.6-omap-h63xx.git] / drivers / ide / pci / hpt34x.c

diff --git a/drivers/ide/pci/hpt34x.c b/drivers/ide/pci/hpt34x.c
index c65971d8d6adc3e50df095f7eb078d9c59e0ef3e..6d2ef0ee0f2b69403615475c8f600f0db54720cf 100644 (file)
--- a/drivers/ide/pci/hpt34x.c
+++ b/drivers/ide/pci/hpt34x.c
@@ -43,15 +43,10 @@
 
 #define HPT343_DEBUG_DRIVE_INFO                0
 
-static u8 hpt34x_ratemask (ide_drive_t *drive)
-{
-       return 1;
-}
-
 static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 {
        struct pci_dev *dev     = HWIF(drive)->pci_dev;
-       u8 speed        = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
+       u8 speed = ide_rate_filter(drive, xferspeed);
        u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
        u8                      hi_speed, lo_speed;
 
@@ -89,41 +84,21 @@ static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
        (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
 }
 
-/*
- * This allows the configuration of ide_pci chipset registers
- * for cards that learn about the drive's UDMA, DMA, PIO capabilities
- * after the drive is reported by the OS.  Initially for designed for
- * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
- */
-
-static int config_chipset_for_dma (ide_drive_t *drive)
-{
-       u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
-
-       if (!(speed))
-               return 0;
-
-       (void) hpt34x_tune_chipset(drive, speed);
-       return ide_dma_enable(drive);
-}
-
 static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
 {
-       ide_hwif_t *hwif        = HWIF(drive);
-
        drive->init_speed = 0;
 
-       if (ide_use_dma(drive) && config_chipset_for_dma(drive))
+       if (ide_tune_dma(drive))
 #ifndef CONFIG_HPT34X_AUTODMA
-               return hwif->ide_dma_off_quietly(drive);
+               return -1;
 #else
-               return hwif->ide_dma_on(drive);
+               return 0;
 #endif
 
        if (ide_use_fast_pio(drive))
                hpt34x_tune_drive(drive, 255);
 
-       return hwif->ide_dma_off_quietly(drive);
+       return -1;
 }
 
 /*
@@ -145,17 +120,10 @@ static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const cha
        pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
 
-       if (cmd & PCI_COMMAND_MEMORY) {
-               if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
-                       pci_write_config_dword(dev, PCI_ROM_ADDRESS,
-                               dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
-                       printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
-                               (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
-               }
+       if (cmd & PCI_COMMAND_MEMORY)
                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
-       } else {
+       else
                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
-       }
 
        /*
         * Since 20-23 can be assigned and are R/W, we correct them.
@@ -207,7 +175,6 @@ static ide_pci_device_t hpt34x_chipset __devinitdata = {
        .name           = "HPT34X",
        .init_chipset   = init_chipset_hpt34x,
        .init_hwif      = init_hwif_hpt34x,
-       .channels       = 2,
        .autodma        = NOAUTODMA,
        .bootable       = NEVER_BOARD,
        .extra          = 16