/*
- * linux/drivers/ide/pci/piix.c Version 0.52 Jul 14, 2007
+ * linux/drivers/ide/pci/piix.c Version 0.54 Sep 5, 2007
*
* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
int u_speed = 0;
int sitre;
u16 reg4042, reg4a;
- u8 reg48, reg54, reg55, pio;
+ u8 reg48, reg54, reg55;
pci_read_config_word(dev, maslave, ®4042);
sitre = (reg4042 & 0x4000) ? 1 : 0;
pci_write_config_byte(dev, 0x54, reg54 | v_flag);
} else
pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
-
- pio = 4;
} else {
const u8 mwdma_to_pio[] = { 0, 3, 4 };
+ u8 pio;
if (reg48 & u_flag)
pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
else
pio = 2; /* only SWDMA2 is allowed */
- }
-
- piix_set_pio_mode(drive, pio);
-}
-
-/**
- * piix_config_drive_xfer_rate - set up an IDE device
- * @drive: IDE drive to configure
- *
- * Set up the PIIX interface for the best available speed on this
- * interface, preferring DMA to PIO.
- */
-
-static int piix_config_drive_xfer_rate (ide_drive_t *drive)
-{
- if (ide_tune_dma(drive))
- return 0;
-
- ide_set_max_pio(drive);
- return -1;
-}
-
-/**
- * piix_is_ichx - check if ICHx
- * @dev: PCI device to check
- *
- * returns 1 if ICHx, 0 otherwise.
- */
-static int piix_is_ichx(struct pci_dev *dev)
-{
- switch (dev->device) {
- case PCI_DEVICE_ID_INTEL_82801EB_1:
- case PCI_DEVICE_ID_INTEL_82801AA_1:
- case PCI_DEVICE_ID_INTEL_82801AB_1:
- case PCI_DEVICE_ID_INTEL_82801BA_8:
- case PCI_DEVICE_ID_INTEL_82801BA_9:
- case PCI_DEVICE_ID_INTEL_82801CA_10:
- case PCI_DEVICE_ID_INTEL_82801CA_11:
- case PCI_DEVICE_ID_INTEL_82801DB_1:
- case PCI_DEVICE_ID_INTEL_82801DB_10:
- case PCI_DEVICE_ID_INTEL_82801DB_11:
- case PCI_DEVICE_ID_INTEL_82801EB_11:
- case PCI_DEVICE_ID_INTEL_82801E_11:
- case PCI_DEVICE_ID_INTEL_ESB_2:
- case PCI_DEVICE_ID_INTEL_ICH6_19:
- case PCI_DEVICE_ID_INTEL_ICH7_21:
- case PCI_DEVICE_ID_INTEL_ESB2_18:
- case PCI_DEVICE_ID_INTEL_ICH8_6:
- return 1;
+ piix_set_pio_mode(drive, pio);
}
-
- return 0;
}
/**
- * init_chipset_piix - set up the PIIX chipset
+ * init_chipset_ich - set up the ICH chipset
* @dev: PCI device to set up
* @name: Name of the device
*
- * Initialize the PCI device as required. For the PIIX this turns
- * out to be nice and simple
+ * Initialize the PCI device as required. For the ICH this turns
+ * out to be nice and simple.
*/
-static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
+static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
{
- if (piix_is_ichx(dev)) {
- unsigned int extra = 0;
- pci_read_config_dword(dev, 0x54, &extra);
- pci_write_config_dword(dev, 0x54, extra|0x400);
- }
+ u32 extra = 0;
+
+ pci_read_config_dword(dev, 0x54, &extra);
+ pci_write_config_dword(dev, 0x54, extra | 0x400);
return 0;
}
u8 dma_stat;
/* clear the INTR & ERROR bits */
- dma_stat = hwif->INB(hwif->dma_status);
+ dma_stat = inb(hwif->dma_status);
/* Should we force the bit as well ? */
- hwif->OUTB(dma_stat, hwif->dma_status);
+ outb(dma_stat, hwif->dma_status);
}
struct ich_laptop {
static const struct ich_laptop ich_laptop[] = {
/* devid, subvendor, subdev */
+ { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
static void __devinit init_hwif_piix(ide_hwif_t *hwif)
{
-#ifndef CONFIG_IA64
- if (!hwif->irq)
- hwif->irq = hwif->channel ? 15 : 14;
-#endif /* CONFIG_IA64 */
-
- if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
- /* This is a painful system best to let it self tune for now */
- return;
- }
-
- hwif->autodma = 0;
-
hwif->set_pio_mode = &piix_set_pio_mode;
hwif->set_dma_mode = &piix_set_dma_mode;
- hwif->drives[0].autotune = 1;
- hwif->drives[1].autotune = 1;
-
if (!hwif->dma_base)
return;
- /* ICHx need to clear the bmdma status for all interrupts */
- if (piix_is_ichx(hwif->pci_dev))
- hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
-
- hwif->atapi_dma = 1;
-
- hwif->ultra_mask = hwif->cds->udma_mask;
- hwif->mwdma_mask = 0x06;
- hwif->swdma_mask = 0x04;
-
if (hwif->ultra_mask & 0x78) {
if (hwif->cbl != ATA_CBL_PATA40_SHORT)
hwif->cbl = piix_cable_detect(hwif);
if (no_piix_dma)
hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
+}
- hwif->ide_dma_check = &piix_config_drive_xfer_rate;
- if (!noautodma)
- hwif->autodma = 1;
+static void __devinit init_hwif_ich(ide_hwif_t *hwif)
+{
+ init_hwif_piix(hwif);
- hwif->drives[1].autodma = hwif->autodma;
- hwif->drives[0].autodma = hwif->autodma;
+ /* ICHx need to clear the BMDMA status for all interrupts */
+ if (hwif->dma_base)
+ hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
}
+#ifndef CONFIG_IA64
+ #define IDE_HFLAGS_PIIX (IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE)
+#else
+ #define IDE_HFLAGS_PIIX IDE_HFLAG_BOOTABLE
+#endif
+
#define DECLARE_PIIX_DEV(name_str, udma) \
{ \
.name = name_str, \
- .init_chipset = init_chipset_piix, \
.init_hwif = init_hwif_piix, \
- .autodma = AUTODMA, \
.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
- .bootable = ON_BOARD, \
+ .host_flags = IDE_HFLAGS_PIIX, \
.pio_mask = ATA_PIO4, \
+ .swdma_mask = ATA_SWDMA2_ONLY, \
+ .mwdma_mask = ATA_MWDMA12_ONLY, \
.udma_mask = udma, \
}
-static ide_pci_device_t piix_pci_info[] __devinitdata = {
- /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
- /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
+#define DECLARE_ICH_DEV(name_str, udma) \
+ { \
+ .name = name_str, \
+ .init_chipset = init_chipset_ich, \
+ .init_hwif = init_hwif_ich, \
+ .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
+ .host_flags = IDE_HFLAGS_PIIX, \
+ .pio_mask = ATA_PIO4, \
+ .swdma_mask = ATA_SWDMA2_ONLY, \
+ .mwdma_mask = ATA_MWDMA12_ONLY, \
+ .udma_mask = udma, \
+ }
+
+static const struct ide_port_info piix_pci_info[] __devinitdata = {
+ /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
+ /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
/* 2 */
{ /*
* of the bit 14 of the IDETIM register at offset 0x6c
*/
.name = "MPIIX",
- .init_hwif = init_hwif_piix,
- .autodma = NODMA,
.enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
- .bootable = ON_BOARD,
- .host_flags = IDE_HFLAG_ISA_PORTS,
+ .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
+ IDE_HFLAGS_PIIX,
.pio_mask = ATA_PIO4,
+ /* This is a painful system best to let it self tune for now */
},
- /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
- /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
- /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */
- /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
- /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */
- /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */
- /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
- /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */
- /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */
- /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */
- /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */
- /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
- /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
- /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */
- /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
- /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */
- /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
- /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */
- /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */
- /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
- /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */
- /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */
+ /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
+ /* 4 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
+ /* 5 */ DECLARE_ICH_DEV("ICH0", ATA_UDMA2),
+ /* 6 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
+ /* 7 */ DECLARE_ICH_DEV("ICH", ATA_UDMA4),
+ /* 8 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA4),
+ /* 9 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
+ /* 10 */ DECLARE_ICH_DEV("ICH2", ATA_UDMA5),
+ /* 11 */ DECLARE_ICH_DEV("ICH2M", ATA_UDMA5),
+ /* 12 */ DECLARE_ICH_DEV("ICH3M", ATA_UDMA5),
+ /* 13 */ DECLARE_ICH_DEV("ICH3", ATA_UDMA5),
+ /* 14 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
+ /* 15 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
+ /* 16 */ DECLARE_ICH_DEV("C-ICH", ATA_UDMA5),
+ /* 17 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
+ /* 18 */ DECLARE_ICH_DEV("ICH5-SATA", ATA_UDMA5),
+ /* 19 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
+ /* 20 */ DECLARE_ICH_DEV("ICH6", ATA_UDMA5),
+ /* 21 */ DECLARE_ICH_DEV("ICH7", ATA_UDMA5),
+ /* 22 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
+ /* 23 */ DECLARE_ICH_DEV("ESB2", ATA_UDMA5),
+ /* 24 */ DECLARE_ICH_DEV("ICH8M", ATA_UDMA5),
};
/**
static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
- ide_pci_device_t *d = &piix_pci_info[id->driver_data];
-
- return ide_setup_pci_device(dev, d);
+ return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
}
/**
printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
}
-static struct pci_device_id piix_pci_tbl[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
+static const struct pci_device_id piix_pci_tbl[] = {
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 0 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 2 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 3 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 4 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 5 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 6 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 7 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 8 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 9 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 10 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 11 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 16 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
#ifdef CONFIG_BLK_DEV_IDE_SATA
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 18 },
#endif
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24},
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 19 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 20 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 21 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 22 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 23 },
+ { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 24 },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);