sl82c105: add PIO autotune fallback to ->ide_dma_check

[linux-2.6-omap-h63xx.git] / drivers / ide / pci / scc_pata.c

diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c
index f668d235e6be25a2a91de82dd18d052ad08b1887..f839bdeb903b0e75b9f653a376154de9b1304abc 100644 (file)
--- a/drivers/ide/pci/scc_pata.c
+++ b/drivers/ide/pci/scc_pata.c
@@ -190,15 +190,15 @@ scc_ide_outsl(unsigned long port, void *addr, u32 count)
 }
 
 /**
- *     scc_tuneproc    -       tune a drive PIO mode
- *     @drive: drive to tune
- *     @mode_wanted: the target operating mode
+ *     scc_set_pio_mode        -       set host controller for PIO mode
+ *     @drive: drive
+ *     @pio: PIO mode number
  *
  *     Load the timing settings for this device mode into the
  *     controller.
  */
 
-static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
+static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
 {
        ide_hwif_t *hwif = HWIF(drive);
        struct scc_ports *ports = ide_get_hwifdata(hwif);
@@ -207,56 +207,32 @@ static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
        unsigned long piosht_port = ctl_base + 0x000;
        unsigned long pioct_port = ctl_base + 0x004;
        unsigned long reg;
-       unsigned char speed = XFER_PIO_0;
        int offset;
 
-       mode_wanted = ide_get_best_pio_mode(drive, mode_wanted, 4);
-       switch (mode_wanted) {
-       case 4:
-               speed = XFER_PIO_4;
-               break;
-       case 3:
-               speed = XFER_PIO_3;
-               break;
-       case 2:
-               speed = XFER_PIO_2;
-               break;
-       case 1:
-               speed = XFER_PIO_1;
-               break;
-       case 0:
-       default:
-               speed = XFER_PIO_0;
-               break;
-       }
-
        reg = in_be32((void __iomem *)cckctrl_port);
        if (reg & CCKCTRL_ATACLKOEN) {
                offset = 1; /* 133MHz */
        } else {
                offset = 0; /* 100MHz */
        }
-       reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
+       reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
        out_be32((void __iomem *)piosht_port, reg);
-       reg = JCHCTtbl[offset][mode_wanted];
+       reg = JCHCTtbl[offset][pio];
        out_be32((void __iomem *)pioct_port, reg);
-
-       ide_config_drive_speed(drive, speed);
 }
 
 /**
- *     scc_tune_chipset        -       tune a drive DMA mode
- *     @drive: Drive to set up
- *     @xferspeed: speed we want to achieve
+ *     scc_set_dma_mode        -       set host controller for DMA mode
+ *     @drive: drive
+ *     @speed: DMA mode
  *
  *     Load the timing settings for this device mode into the
  *     controller.
  */
 
-static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
+static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
 {
        ide_hwif_t *hwif = HWIF(drive);
-       u8 speed = ide_rate_filter(drive, xferspeed);
        struct scc_ports *ports = ide_get_hwifdata(hwif);
        unsigned long ctl_base = ports->ctl;
        unsigned long cckctrl_port = ctl_base + 0xff0;
@@ -280,28 +256,16 @@ static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
 
        switch (speed) {
        case XFER_UDMA_6:
-               idx = 6;
-               break;
        case XFER_UDMA_5:
-               idx = 5;
-               break;
        case XFER_UDMA_4:
-               idx = 4;
-               break;
        case XFER_UDMA_3:
-               idx = 3;
-               break;
        case XFER_UDMA_2:
-               idx = 2;
-               break;
        case XFER_UDMA_1:
-               idx = 1;
-               break;
        case XFER_UDMA_0:
-               idx = 0;
+               idx = speed - XFER_UDMA_0;
                break;
        default:
-               return 1;
+               return;
        }
 
        jcactsel = JCACTSELtbl[offset][idx];
@@ -317,8 +281,6 @@ static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
        }
        reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
        out_be32((void __iomem *)udenvt_port, reg);
-
-       return ide_config_drive_speed(drive, speed);
 }
 
 /**
@@ -329,7 +291,7 @@ static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
  *     required.
  *      If the drive isn't suitable for DMA or we hit other problems
  *      then we will drop down to PIO and set up PIO appropriately.
- *      (return 1)
+ *      (return -1)
  */
 
 static int scc_config_drive_for_dma(ide_drive_t *drive)
@@ -337,8 +299,7 @@ static int scc_config_drive_for_dma(ide_drive_t *drive)
        if (ide_tune_dma(drive))
                return 0;
 
-       if (ide_use_fast_pio(drive))
-               scc_tuneproc(drive, 4);
+       ide_set_max_pio(drive);
 
        return -1;
 }
@@ -551,8 +512,8 @@ static int setup_mmio_scc (struct pci_dev *dev, const char *name)
        unsigned long dma_base = pci_resource_start(dev, 1);
        unsigned long ctl_size = pci_resource_len(dev, 0);
        unsigned long dma_size = pci_resource_len(dev, 1);
-       void *ctl_addr;
-       void *dma_addr;
+       void __iomem *ctl_addr;
+       void __iomem *dma_addr;
        int i;
 
        for (i = 0; i < MAX_HWIFS; i++) {
@@ -738,8 +699,8 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 
        hwif->dma_setup = scc_dma_setup;
        hwif->ide_dma_end = scc_ide_dma_end;
-       hwif->speedproc = scc_tune_chipset;
-       hwif->tuneproc = scc_tuneproc;
+       hwif->set_pio_mode = scc_set_pio_mode;
+       hwif->set_dma_mode = scc_set_dma_mode;
        hwif->ide_dma_check = scc_config_drive_for_dma;
        hwif->ide_dma_test_irq = scc_dma_test_irq;
        hwif->udma_filter = scc_udma_filter;