/*
- Driver for Zarlink VP310/MT312 Satellite Channel Decoder
+ Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
+ Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
struct dvb_frontend frontend;
u8 id;
- u8 frequency;
+ unsigned long xtal;
+ u8 freq_mult;
};
static int debug;
printk(KERN_DEBUG "mt312: " args); \
} while (0)
-#define MT312_SYS_CLK 90000000UL /* 90 MHz */
-#define MT312_LPOWER_SYS_CLK 60000000UL /* 60 MHz */
#define MT312_PLL_CLK 10000000UL /* 10 MHz */
+#define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */
static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
- void *buf, const size_t count)
+ u8 *buf, const size_t count)
{
int ret;
struct i2c_msg msg[2];
ret = i2c_transfer(state->i2c, msg, 2);
if (ret != 2) {
- printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
+ printk(KERN_ERR "%s: ret == %d\n", __func__, ret);
return -EREMOTEIO;
}
int i;
dprintk("R(%d):", reg & 0x7f);
for (i = 0; i < count; i++)
- printk(" %02x", ((const u8 *) buf)[i]);
+ printk(" %02x", buf[i]);
printk("\n");
}
}
static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
- const void *src, const size_t count)
+ const u8 *src, const size_t count)
{
int ret;
u8 buf[count + 1];
int i;
dprintk("W(%d):", reg & 0x7f);
for (i = 0; i < count; i++)
- printk(" %02x", ((const u8 *) src)[i]);
+ printk(" %02x", src[i]);
printk("\n");
}
ret = i2c_transfer(state->i2c, &msg, 1);
if (ret != 1) {
- dprintk("%s: ret == %d\n", __FUNCTION__, ret);
+ dprintk("%s: ret == %d\n", __func__, ret);
return -EREMOTEIO;
}
int ret;
u8 vit_mode;
- if ((ret = mt312_readreg(state, VIT_MODE, &vit_mode)) < 0)
+ ret = mt312_readreg(state, VIT_MODE, &vit_mode);
+ if (ret < 0)
return ret;
if (vit_mode & 0x80) /* auto inversion was used */
u16 monitor;
u8 buf[2];
- if ((ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h)) < 0)
+ ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
+ if (ret < 0)
return ret;
if (sym_rate_h & 0x80) {
/* symbol rate search was used */
- if ((ret = mt312_writereg(state, MON_CTRL, 0x03)) < 0)
+ ret = mt312_writereg(state, MON_CTRL, 0x03);
+ if (ret < 0)
return ret;
- if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
+ ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
+ if (ret < 0)
return ret;
monitor = (buf[0] << 8) | buf[1];
dprintk("sr(auto) = %u\n",
mt312_div(monitor * 15625, 4));
} else {
- if ((ret = mt312_writereg(state, MON_CTRL, 0x05)) < 0)
+ ret = mt312_writereg(state, MON_CTRL, 0x05);
+ if (ret < 0)
return ret;
- if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
+ ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
+ if (ret < 0)
return ret;
dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
- if ((ret = mt312_read(state, SYM_RAT_OP_H, buf,
- sizeof(buf))) < 0)
+ ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
+ if (ret < 0)
return ret;
sym_rat_op = (buf[0] << 8) | buf[1];
dprintk("sym_rat_op=%d dec_ratio=%d\n",
sym_rat_op, dec_ratio);
dprintk("*sr(manual) = %lu\n",
- (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
+ (((state->xtal * 8192) / (sym_rat_op + 8192)) *
2) - dec_ratio);
}
int ret;
u8 fec_status;
- if ((ret = mt312_readreg(state, FEC_STATUS, &fec_status)) < 0)
+ ret = mt312_readreg(state, FEC_STATUS, &fec_status);
+ if (ret < 0)
return ret;
*cr = fec_tab[(fec_status >> 4) & 0x07];
u8 buf[2];
/* wake up */
- if ((ret = mt312_writereg(state, CONFIG,
- (state->frequency == 60 ? 0x88 : 0x8c))) < 0)
+ ret = mt312_writereg(state, CONFIG,
+ (state->freq_mult == 6 ? 0x88 : 0x8c));
+ if (ret < 0)
return ret;
/* wait at least 150 usec */
udelay(150);
/* full reset */
- if ((ret = mt312_reset(state, 1)) < 0)
+ ret = mt312_reset(state, 1);
+ if (ret < 0)
return ret;
/* Per datasheet, write correct values. 09/28/03 ACCJr.
u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
0x01, 0x00, 0x00, 0x00 };
- if ((ret = mt312_write(state, VIT_SETUP, buf_def,
- sizeof(buf_def))) < 0)
+ ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
+ if (ret < 0)
return ret;
}
+ switch (state->id) {
+ case ID_ZL10313:
+ /* enable ADC */
+ ret = mt312_writereg(state, GPP_CTRL, 0x80);
+ if (ret < 0)
+ return ret;
+
+ /* configure ZL10313 for optimal ADC performance */
+ buf[0] = 0x80;
+ buf[1] = 0xB0;
+ ret = mt312_write(state, HW_CTRL, buf, 2);
+ if (ret < 0)
+ return ret;
+
+ /* enable MPEG output and ADCs */
+ ret = mt312_writereg(state, HW_CTRL, 0x00);
+ if (ret < 0)
+ return ret;
+
+ ret = mt312_writereg(state, MPEG_CTRL, 0x00);
+ if (ret < 0)
+ return ret;
+
+ break;
+ }
+
/* SYS_CLK */
- buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK :
- MT312_SYS_CLK) * 2, 1000000);
+ buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
/* DISEQC_RATIO */
- buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
+ buf[1] = mt312_div(state->xtal, 22000 * 4);
- if ((ret = mt312_write(state, SYS_CLK, buf, sizeof(buf))) < 0)
+ ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
+ if (ret < 0)
return ret;
- if ((ret = mt312_writereg(state, SNR_THS_HIGH, 0x32)) < 0)
+ ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
+ if (ret < 0)
return ret;
- if ((ret = mt312_writereg(state, OP_CTRL, 0x53)) < 0)
+ /* different MOCLK polarity */
+ switch (state->id) {
+ case ID_ZL10313:
+ buf[0] = 0x33;
+ break;
+ default:
+ buf[0] = 0x53;
+ break;
+ }
+
+ ret = mt312_writereg(state, OP_CTRL, buf[0]);
+ if (ret < 0)
return ret;
/* TS_SW_LIM */
buf[0] = 0x8c;
buf[1] = 0x98;
- if ((ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf))) < 0)
+ ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
+ if (ret < 0)
return ret;
- if ((ret = mt312_writereg(state, CS_SW_LIM, 0x69)) < 0)
+ ret = mt312_writereg(state, CS_SW_LIM, 0x69);
+ if (ret < 0)
return ret;
return 0;
if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
return -EINVAL;
- if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
+ ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
+ if (ret < 0)
return ret;
- if ((ret =
- mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)
+ ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
+ if (ret < 0)
return ret;
- if ((ret =
- mt312_writereg(state, DISEQC_MODE,
- (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
- | 0x04)) < 0)
+ ret = mt312_writereg(state, DISEQC_MODE,
+ (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
+ | 0x04);
+ if (ret < 0)
return ret;
+ /* is there a better way to wait for message to be transmitted */
+ msleep(100);
+
/* set DISEQC_MODE[2:0] to zero if a return message is expected */
- if (c->msg[0] & 0x02)
- if ((ret = mt312_writereg(state, DISEQC_MODE,
- (diseqc_mode & 0x40))) < 0)
+ if (c->msg[0] & 0x02) {
+ ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
+ if (ret < 0)
return ret;
+ }
return 0;
}
if (c > SEC_MINI_B)
return -EINVAL;
- if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
+ ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
+ if (ret < 0)
return ret;
- if ((ret =
- mt312_writereg(state, DISEQC_MODE,
- (diseqc_mode & 0x40) | mini_tab[c])) < 0)
+ ret = mt312_writereg(state, DISEQC_MODE,
+ (diseqc_mode & 0x40) | mini_tab[c]);
+ if (ret < 0)
return ret;
return 0;
if (t > SEC_TONE_OFF)
return -EINVAL;
- if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
+ ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
+ if (ret < 0)
return ret;
- if ((ret =
- mt312_writereg(state, DISEQC_MODE,
- (diseqc_mode & 0x40) | tone_tab[t])) < 0)
+ ret = mt312_writereg(state, DISEQC_MODE,
+ (diseqc_mode & 0x40) | tone_tab[t]);
+ if (ret < 0)
return ret;
return 0;
{
struct mt312_state *state = fe->demodulator_priv;
const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
+ u8 val;
if (v > SEC_VOLTAGE_OFF)
return -EINVAL;
- return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
+ val = volt_tab[v];
+ if (state->config->voltage_inverted)
+ val ^= 0x40;
+
+ return mt312_writereg(state, DISEQC_MODE, val);
}
static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s)
*s = 0;
- if ((ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status))) < 0)
+ ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
+ if (ret < 0)
return ret;
dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
int ret;
u8 buf[3];
- if ((ret = mt312_read(state, RS_BERCNT_H, buf, 3)) < 0)
+ ret = mt312_read(state, RS_BERCNT_H, buf, 3);
+ if (ret < 0)
return ret;
*ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
u16 agc;
s16 err_db;
- if ((ret = mt312_read(state, AGC_H, buf, sizeof(buf))) < 0)
+ ret = mt312_read(state, AGC_H, buf, sizeof(buf));
+ if (ret < 0)
return ret;
agc = (buf[0] << 6) | (buf[1] >> 2);
int ret;
u8 buf[2];
- if ((ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf))) < 0)
+ ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
+ if (ret < 0)
return ret;
*snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
int ret;
u8 buf[2];
- if ((ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf))) < 0)
+ ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
+ if (ret < 0)
return ret;
*ubc = (buf[0] << 8) | buf[1];
{ 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
- dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency);
+ dprintk("%s: Freq %d\n", __func__, p->frequency);
if ((p->frequency < fe->ops.info.frequency_min)
|| (p->frequency > fe->ops.info.frequency_max))
return ret;
if (p->u.qpsk.symbol_rate >= 30000000) {
/* Note that 30MS/s should use 90MHz */
- if ((config_val & 0x0c) == 0x08) {
+ if (state->freq_mult == 6) {
/* We are running 60MHz */
- state->frequency = 90;
- if ((ret = mt312_initfe(fe)) < 0)
+ state->freq_mult = 9;
+ ret = mt312_initfe(fe);
+ if (ret < 0)
return ret;
}
} else {
- if ((config_val & 0x0c) == 0x0C) {
+ if (state->freq_mult == 9) {
/* We are running 90MHz */
- state->frequency = 60;
- if ((ret = mt312_initfe(fe)) < 0)
+ state->freq_mult = 6;
+ ret = mt312_initfe(fe);
+ if (ret < 0)
return ret;
}
}
break;
case ID_MT312:
+ case ID_ZL10313:
break;
default:
/* GO */
buf[4] = 0x01;
- if ((ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf))) < 0)
+ ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
+ if (ret < 0)
return ret;
mt312_reset(state, 0);
struct mt312_state *state = fe->demodulator_priv;
int ret;
- if ((ret = mt312_get_inversion(state, &p->inversion)) < 0)
+ ret = mt312_get_inversion(state, &p->inversion);
+ if (ret < 0)
return ret;
- if ((ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate)) < 0)
+ ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate);
+ if (ret < 0)
return ret;
- if ((ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner)) < 0)
+ ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner);
+ if (ret < 0)
return ret;
return 0;
{
struct mt312_state *state = fe->demodulator_priv;
- if (enable) {
- return mt312_writereg(state, GPP_CTRL, 0x40);
- } else {
- return mt312_writereg(state, GPP_CTRL, 0x00);
+ u8 val = 0x00;
+ int ret;
+
+ switch (state->id) {
+ case ID_ZL10313:
+ ret = mt312_readreg(state, GPP_CTRL, &val);
+ if (ret < 0)
+ goto error;
+
+ /* preserve this bit to not accidently shutdown ADC */
+ val &= 0x80;
+ break;
}
+
+ if (enable)
+ val |= 0x40;
+ else
+ val &= ~0x40;
+
+ ret = mt312_writereg(state, GPP_CTRL, val);
+
+error:
+ return ret;
}
static int mt312_sleep(struct dvb_frontend *fe)
u8 config;
/* reset all registers to defaults */
- if ((ret = mt312_reset(state, 1)) < 0)
+ ret = mt312_reset(state, 1);
+ if (ret < 0)
return ret;
- if ((ret = mt312_readreg(state, CONFIG, &config)) < 0)
+ if (state->id == ID_ZL10313) {
+ /* reset ADC */
+ ret = mt312_writereg(state, GPP_CTRL, 0x00);
+ if (ret < 0)
+ return ret;
+
+ /* full shutdown of ADCs, mpeg bus tristated */
+ ret = mt312_writereg(state, HW_CTRL, 0x0d);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = mt312_readreg(state, CONFIG, &config);
+ if (ret < 0)
return ret;
/* enter standby */
- if ((ret = mt312_writereg(state, CONFIG, config & 0x7f)) < 0)
+ ret = mt312_writereg(state, CONFIG, config & 0x7f);
+ if (ret < 0)
return ret;
return 0;
kfree(state);
}
+#define MT312_SYS_CLK 90000000UL /* 90 MHz */
static struct dvb_frontend_ops vp310_mt312_ops = {
.info = {
.type = FE_QPSK,
.frequency_min = 950000,
.frequency_max = 2150000,
- .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
- .symbol_rate_min = MT312_SYS_CLK / 128,
+ .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, /* FIXME: adjust freq to real used xtal */
+ .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
.symbol_rate_max = MT312_SYS_CLK / 2,
.caps =
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
switch (state->id) {
case ID_VP310:
strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
- state->frequency = 90;
+ state->xtal = MT312_PLL_CLK;
+ state->freq_mult = 9;
break;
case ID_MT312:
strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
- state->frequency = 60;
+ state->xtal = MT312_PLL_CLK;
+ state->freq_mult = 6;
+ break;
+ case ID_ZL10313:
+ strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S");
+ state->xtal = MT312_PLL_CLK_10_111;
+ state->freq_mult = 9;
break;
default:
- printk(KERN_WARNING "Only Zarlink VP310/MT312"
+ printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313"
" are supported chips.\n");
goto error;
}
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
-MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
+MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
MODULE_LICENSE("GPL");
projects / linux-2.6-omap-h63xx.git / blobdiff