#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/ndfc.h>
-#include <linux/mtd/ubi.h>
#include <linux/mtd/mtd.h>
#include <linux/platform_device.h>
writel(ccr, ndfc->ndfcbase + NDFC_CCR);
}
-static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd)
+static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct ndfc_controller *ndfc = &ndfc_ctrl;
- struct nand_chip *chip = mtd->priv;
-
- switch (cmd) {
- case NAND_CTL_SETCLE:
- chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_CMD;
- break;
- case NAND_CTL_SETALE:
- chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_ALE;
- break;
- default:
- chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
- break;
- }
+
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
+ else
+ writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
}
static int ndfc_ready(struct mtd_info *mtd)
chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
- chip->hwcontrol = ndfc_hwcontrol;
+ chip->cmd_ctrl = ndfc_hwcontrol;
chip->dev_ready = ndfc_ready;
chip->select_chip = ndfc_select_chip;
chip->chip_delay = 50;
chip->read_buf = ndfc_read_buf;
chip->write_buf = ndfc_write_buf;
chip->verify_buf = ndfc_verify_buf;
- chip->correct_data = nand_correct_data;
- chip->enable_hwecc = ndfc_enable_hwecc;
- chip->calculate_ecc = ndfc_calculate_ecc;
- chip->eccmode = NAND_ECC_HW3_256;
- chip->autooob = mtd->pl_chip->autooob;
+ chip->ecc.correct = nand_correct_data;
+ chip->ecc.hwctl = ndfc_enable_hwecc;
+ chip->ecc.calculate = ndfc_calculate_ecc;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.size = 256;
+ chip->ecc.bytes = 3;
+ chip->ecclayout = mtd->pl_chip->ecclayout;
mtd->mtd.priv = chip;
mtd->mtd.owner = THIS_MODULE;
}
static int ndfc_chip_probe(struct platform_device *pdev)
{
- int rc;
struct platform_nand_chip *nc = pdev->dev.platform_data;
struct ndfc_chip_settings *settings = nc->priv;
struct ndfc_controller *ndfc = &ndfc_ctrl;
#ifdef CONFIG_MTD_PARTITIONS
printk("Number of partitions %d\n", nc->nr_partitions);
if (nc->nr_partitions) {
- struct mtd_info *mtd_ubi;
- nc->partitions[NAND_PARTS_CONTENT_IDX].mtdp = &mtd_ubi;
-
- add_mtd_device(&nandmtd->mtd); /* for testing */
- add_mtd_partitions(&nandmtd->mtd,
- nc->partitions,
+ /* Add the full device, so complete dumps can be made */
+ add_mtd_device(&nandmtd->mtd);
+ add_mtd_partitions(&nandmtd->mtd, nc->partitions,
nc->nr_partitions);
- add_mtd_device(mtd_ubi);
-
} else
#else
add_mtd_device(&nandmtd->mtd);
struct ndfc_controller_settings *settings = nc->priv;
struct resource *res = pdev->resource;
struct ndfc_controller *ndfc = &ndfc_ctrl;
- unsigned long long phys = NDFC_PHYSADDR_OFFS | res->start;
+ unsigned long long phys = settings->ndfc_erpn | res->start;
ndfc->ndfcbase = ioremap64(phys, res->end - res->start + 1);
if (!ndfc->ndfcbase) {
static int __init ndfc_nand_init(void)
{
- int ret = platform_driver_register(&ndfc_nand_driver);
+ int ret;
+
+ spin_lock_init(&ndfc_ctrl.ndfc_control.lock);
+ init_waitqueue_head(&ndfc_ctrl.ndfc_control.wq);
+ ret = platform_driver_register(&ndfc_nand_driver);
if (!ret)
ret = platform_driver_register(&ndfc_chip_driver);
return ret;