[MTD NAND] CAFÉ controller depends, perhaps unsurprisingly, on NAND

[linux-2.6-omap-h63xx.git] / drivers / mtd / nand / ppchameleonevb.c

diff --git a/drivers/mtd/nand/ppchameleonevb.c b/drivers/mtd/nand/ppchameleonevb.c
index 5d4d16fb1df63849b592b0b4443e5b3f731503f2..eb7d4d443deb1b7cdcc6480f9653db79a637e6dd 100644 (file)
--- a/drivers/mtd/nand/ppchameleonevb.c
+++ b/drivers/mtd/nand/ppchameleonevb.c
@@ -108,54 +108,68 @@ extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partitio
 /*
  *     hardware specific access to control-lines
  */
-static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+                                 unsigned int ctrl)
 {
-       switch (cmd) {
-
-       case NAND_CTL_SETCLE:
-               MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
-               break;
-       case NAND_CTL_CLRCLE:
-               MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
-               break;
-       case NAND_CTL_SETALE:
-               MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
-               break;
-       case NAND_CTL_CLRALE:
-               MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
-               break;
-       case NAND_CTL_SETNCE:
-               MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
-               break;
-       case NAND_CTL_CLRNCE:
-               MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
-               break;
+       struct nand_chip *chip = mtd->priv;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+#error Missing headerfiles. No way to fix this. -tglx
+               switch (cmd) {
+               case NAND_CTL_SETCLE:
+                       MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
+                       break;
+               case NAND_CTL_CLRCLE:
+                       MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
+                       break;
+               case NAND_CTL_SETALE:
+                       MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
+                       break;
+               case NAND_CTL_CLRALE:
+                       MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
+                       break;
+               case NAND_CTL_SETNCE:
+                       MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
+                       break;
+               case NAND_CTL_CLRNCE:
+                       MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
+                       break;
+               }
        }
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, chip->IO_ADDR_W);
 }
 
-static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+                                    unsigned int ctrl)
 {
-       switch (cmd) {
-
-       case NAND_CTL_SETCLE:
-               MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
-               break;
-       case NAND_CTL_CLRCLE:
-               MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
-               break;
-       case NAND_CTL_SETALE:
-               MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
-               break;
-       case NAND_CTL_CLRALE:
-               MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
-               break;
-       case NAND_CTL_SETNCE:
-               MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
-               break;
-       case NAND_CTL_CLRNCE:
-               MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
-               break;
+       struct nand_chip *chip = mtd->priv;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+#error Missing headerfiles. No way to fix this. -tglx
+               switch (cmd) {
+               case NAND_CTL_SETCLE:
+                       MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
+                       break;
+               case NAND_CTL_CLRCLE:
+                       MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
+                       break;
+               case NAND_CTL_SETALE:
+                       MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
+                       break;
+               case NAND_CTL_CLRALE:
+                       MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
+                       break;
+               case NAND_CTL_SETNCE:
+                       MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
+                       break;
+               case NAND_CTL_CLRNCE:
+                       MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
+                       break;
+               }
        }
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, chip->IO_ADDR_W);
 }
 
 #ifdef USE_READY_BUSY_PIN
@@ -251,17 +265,18 @@ static int __init ppchameleonevb_init(void)
        /* insert callbacks */
        this->IO_ADDR_R = ppchameleon_fio_base;
        this->IO_ADDR_W = ppchameleon_fio_base;
-       this->hwcontrol = ppchameleon_hwcontrol;
+       this->cmd_ctrl = ppchameleon_hwcontrol;
 #ifdef USE_READY_BUSY_PIN
        this->dev_ready = ppchameleon_device_ready;
 #endif
        this->chip_delay = NAND_BIG_DELAY_US;
        /* ECC mode */
-       this->eccmode = NAND_ECC_SOFT;
+       this->ecc.mode = NAND_ECC_SOFT;
 
        /* Scan to find existence of the device (it could not be mounted) */
        if (nand_scan(ppchameleon_mtd, 1)) {
                iounmap((void *)ppchameleon_fio_base);
+               ppchameleon_fio_base = NULL;
                kfree(ppchameleon_mtd);
                goto nand_evb_init;
        }
@@ -300,6 +315,8 @@ static int __init ppchameleonevb_init(void)
        ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
        if (!ppchameleonevb_mtd) {
                printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
+               if (ppchameleon_fio_base)
+                       iounmap(ppchameleon_fio_base);
                return -ENOMEM;
        }
 
@@ -308,6 +325,8 @@ static int __init ppchameleonevb_init(void)
        if (!ppchameleonevb_fio_base) {
                printk("ioremap PPChameleonEVB NAND flash failed\n");
                kfree(ppchameleonevb_mtd);
+               if (ppchameleon_fio_base)
+                       iounmap(ppchameleon_fio_base);
                return -EIO;
        }
 
@@ -351,19 +370,21 @@ static int __init ppchameleonevb_init(void)
        /* insert callbacks */
        this->IO_ADDR_R = ppchameleonevb_fio_base;
        this->IO_ADDR_W = ppchameleonevb_fio_base;
-       this->hwcontrol = ppchameleonevb_hwcontrol;
+       this->cmd_ctrl = ppchameleonevb_hwcontrol;
 #ifdef USE_READY_BUSY_PIN
        this->dev_ready = ppchameleonevb_device_ready;
 #endif
        this->chip_delay = NAND_SMALL_DELAY_US;
 
        /* ECC mode */
-       this->eccmode = NAND_ECC_SOFT;
+       this->ecc.mode = NAND_ECC_SOFT;
 
        /* Scan to find existence of the device */
        if (nand_scan(ppchameleonevb_mtd, 1)) {
                iounmap((void *)ppchameleonevb_fio_base);
                kfree(ppchameleonevb_mtd);
+               if (ppchameleon_fio_base)
+                       iounmap(ppchameleon_fio_base);
                return -ENXIO;
        }
 #ifdef CONFIG_MTD_PARTITIONS