virtio: finer-grained features for virtio_net

[linux-2.6-omap-h63xx.git] / drivers / net / bnx2.c

diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 8af63b4ec67d727284994ec719cc33cf86106fad..15853be4680ae93a1f8c2904c3d41c72d3ca345d 100644 (file)
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -56,15 +56,15 @@
 
 #define DRV_MODULE_NAME                "bnx2"
 #define PFX DRV_MODULE_NAME    ": "
-#define DRV_MODULE_VERSION     "1.7.2"
-#define DRV_MODULE_RELDATE     "January 21, 2008"
+#define DRV_MODULE_VERSION     "1.7.4"
+#define DRV_MODULE_RELDATE     "February 18, 2008"
 
 #define RUN_AT(x) (jiffies + (x))
 
 /* Time in jiffies before concluding the transmitter is hung. */
 #define TX_TIMEOUT  (5*HZ)
 
-static const char version[] __devinitdata =
+static char version[] __devinitdata =
        "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 
 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
@@ -90,7 +90,7 @@ typedef enum {
 } board_t;
 
 /* indexed by board_t, above */
-static const struct {
+static struct {
        char *name;
 } board_info[] __devinitdata = {
        { "Broadcom NetXtreme II BCM5706 1000Base-T" },
@@ -992,6 +992,42 @@ bnx2_copper_linkup(struct bnx2 *bp)
        return 0;
 }
 
+static void
+bnx2_init_rx_context0(struct bnx2 *bp)
+{
+       u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
+
+       val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
+       val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
+       val |= 0x02 << 8;
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               u32 lo_water, hi_water;
+
+               if (bp->flow_ctrl & FLOW_CTRL_TX)
+                       lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
+               else
+                       lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
+               if (lo_water >= bp->rx_ring_size)
+                       lo_water = 0;
+
+               hi_water = bp->rx_ring_size / 4;
+
+               if (hi_water <= lo_water)
+                       lo_water = 0;
+
+               hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
+               lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
+
+               if (hi_water > 0xf)
+                       hi_water = 0xf;
+               else if (hi_water == 0)
+                       lo_water = 0;
+               val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
+       }
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
+}
+
 static int
 bnx2_set_mac_link(struct bnx2 *bp)
 {
@@ -1056,6 +1092,9 @@ bnx2_set_mac_link(struct bnx2 *bp)
        /* Acknowledge the interrupt. */
        REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 
+       if (CHIP_NUM(bp) == CHIP_NUM_5709)
+               bnx2_init_rx_context0(bp);
+
        return 0;
 }
 
@@ -1234,14 +1273,20 @@ bnx2_set_link(struct bnx2 *bp)
 
        if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
            (CHIP_NUM(bp) == CHIP_NUM_5706)) {
-               u32 val;
+               u32 val, an_dbg;
 
                if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
                        bnx2_5706s_force_link_dn(bp, 0);
                        bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
                }
                val = REG_RD(bp, BNX2_EMAC_STATUS);
-               if (val & BNX2_EMAC_STATUS_LINK)
+
+               bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
+               bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
+               bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
+
+               if ((val & BNX2_EMAC_STATUS_LINK) &&
+                   !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
                        bmsr |= BMSR_LSTATUS;
                else
                        bmsr &= ~BMSR_LSTATUS;
@@ -1390,7 +1435,7 @@ bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
 
        if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
                speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
-       if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
+       if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
                speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
 
        if (port == PORT_TP)
@@ -4616,6 +4661,13 @@ bnx2_init_rx_ring(struct bnx2 *bp)
        bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
                             bp->rx_buf_use_size, bp->rx_max_ring);
 
+       bnx2_init_rx_context0(bp);
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
+               REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
+       }
+
        bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
        if (bp->rx_pg_ring_size) {
                bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
@@ -4636,11 +4688,6 @@ bnx2_init_rx_ring(struct bnx2 *bp)
                        REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
        }
 
-       val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
-       val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
-       val |= 0x02 << 8;
-       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
-
        val = (u64) bp->rx_desc_mapping[0] >> 32;
        bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
 
@@ -5315,11 +5362,15 @@ bnx2_test_intr(struct bnx2 *bp)
        return -ENODEV;
 }
 
+/* Determining link for parallel detection. */
 static int
 bnx2_5706_serdes_has_link(struct bnx2 *bp)
 {
        u32 mode_ctl, an_dbg, exp;
 
+       if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
+               return 0;
+
        bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
        bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
 
@@ -5349,13 +5400,6 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
        int check_link = 1;
 
        spin_lock(&bp->phy_lock);
-       if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
-               bnx2_5706s_force_link_dn(bp, 0);
-               bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
-               spin_unlock(&bp->phy_lock);
-               return;
-       }
-
        if (bp->serdes_an_pending) {
                bp->serdes_an_pending--;
                check_link = 0;
@@ -5379,7 +5423,6 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
                 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
                u32 phy2;
 
-               check_link = 0;
                bnx2_write_phy(bp, 0x17, 0x0f01);
                bnx2_read_phy(bp, 0x15, &phy2);
                if (phy2 & 0x20) {
@@ -5394,17 +5437,21 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
        } else
                bp->current_interval = bp->timer_interval;
 
-       if (bp->link_up && (bp->autoneg & AUTONEG_SPEED) && check_link) {
+       if (check_link) {
                u32 val;
 
                bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
                bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
                bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
 
-               if (val & MISC_SHDW_AN_DBG_NOSYNC) {
-                       bnx2_5706s_force_link_dn(bp, 1);
-                       bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
-               }
+               if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
+                       if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
+                               bnx2_5706s_force_link_dn(bp, 1);
+                               bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
+                       } else
+                               bnx2_set_link(bp);
+               } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
+                       bnx2_set_link(bp);
        }
        spin_unlock(&bp->phy_lock);
 }
@@ -7285,7 +7332,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                        bp->flags |= BNX2_FLAG_NO_WOL;
                        bp->wol = 0;
                }
-               if (CHIP_NUM(bp) != CHIP_NUM_5706) {
+               if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+                       /* Don't do parallel detect on this board because of
+                        * some board problems.  The link will not go down
+                        * if we do parallel detect.
+                        */
+                       if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
+                           pdev->subsystem_device == 0x310c)
+                               bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
+               } else {
                        bp->phy_addr = 2;
                        if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
                                bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;