]> pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - drivers/net/bnx2.c
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.26
[linux-2.6-omap-h63xx.git] / drivers / net / bnx2.c
index 65812870c5acb833f22e02716cebaf14469ba700..4b46e68183e059fbddb9eb6c007fcab7894e68b2 100644 (file)
 
 #define DRV_MODULE_NAME                "bnx2"
 #define PFX DRV_MODULE_NAME    ": "
-#define DRV_MODULE_VERSION     "1.7.2"
-#define DRV_MODULE_RELDATE     "January 21, 2008"
+#define DRV_MODULE_VERSION     "1.7.5"
+#define DRV_MODULE_RELDATE     "April 29, 2008"
 
 #define RUN_AT(x) (jiffies + (x))
 
 /* Time in jiffies before concluding the transmitter is hung. */
 #define TX_TIMEOUT  (5*HZ)
 
-static const char version[] __devinitdata =
+static char version[] __devinitdata =
        "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 
 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
@@ -90,7 +90,7 @@ typedef enum {
 } board_t;
 
 /* indexed by board_t, above */
-static const struct {
+static struct {
        char *name;
 } board_info[] __devinitdata = {
        { "Broadcom NetXtreme II BCM5706 1000Base-T" },
@@ -265,6 +265,18 @@ bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
        spin_unlock_bh(&bp->indirect_lock);
 }
 
+static void
+bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
+{
+       bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
+}
+
+static u32
+bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
+{
+       return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
+}
+
 static void
 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 {
@@ -296,7 +308,7 @@ bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
        u32 val1;
        int i, ret;
 
-       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
                val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
                val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 
@@ -334,7 +346,7 @@ bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
                ret = 0;
        }
 
-       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
                val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
                val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 
@@ -353,7 +365,7 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
        u32 val1;
        int i, ret;
 
-       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
                val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
                val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 
@@ -383,7 +395,7 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
        else
                ret = 0;
 
-       if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
                val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
                val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 
@@ -580,7 +592,7 @@ bnx2_alloc_mem(struct bnx2 *bp)
 
        /* Combine status and statistics blocks into one allocation. */
        status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
-       if (bp->flags & MSIX_CAP_FLAG)
+       if (bp->flags & BNX2_FLAG_MSIX_CAP)
                status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
                                                 BNX2_SBLK_MSIX_ALIGN_SIZE);
        bp->status_stats_size = status_blk_size +
@@ -594,7 +606,7 @@ bnx2_alloc_mem(struct bnx2 *bp)
        memset(bp->status_blk, 0, bp->status_stats_size);
 
        bp->bnx2_napi[0].status_blk = bp->status_blk;
-       if (bp->flags & MSIX_CAP_FLAG) {
+       if (bp->flags & BNX2_FLAG_MSIX_CAP) {
                for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
                        struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 
@@ -634,7 +646,7 @@ bnx2_report_fw_link(struct bnx2 *bp)
 {
        u32 fw_link_status = 0;
 
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                return;
 
        if (bp->link_up) {
@@ -676,7 +688,7 @@ bnx2_report_fw_link(struct bnx2 *bp)
                        bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 
                        if (!(bmsr & BMSR_ANEGCOMPLETE) ||
-                           bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
+                           bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
                                fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
                        else
                                fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
@@ -685,14 +697,14 @@ bnx2_report_fw_link(struct bnx2 *bp)
        else
                fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 
-       REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
+       bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 }
 
 static char *
 bnx2_xceiver_str(struct bnx2 *bp)
 {
        return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
-               ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
+               ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
                 "Copper"));
 }
 
@@ -752,7 +764,7 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
                return;
        }
 
-       if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+       if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
            (CHIP_NUM(bp) == CHIP_NUM_5708)) {
                u32 val;
 
@@ -767,7 +779,7 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
        bnx2_read_phy(bp, bp->mii_adv, &local_adv);
        bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 
-       if (bp->phy_flags & PHY_SERDES_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                u32 new_local_adv = 0;
                u32 new_remote_adv = 0;
 
@@ -980,6 +992,42 @@ bnx2_copper_linkup(struct bnx2 *bp)
        return 0;
 }
 
+static void
+bnx2_init_rx_context0(struct bnx2 *bp)
+{
+       u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
+
+       val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
+       val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
+       val |= 0x02 << 8;
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               u32 lo_water, hi_water;
+
+               if (bp->flow_ctrl & FLOW_CTRL_TX)
+                       lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
+               else
+                       lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
+               if (lo_water >= bp->rx_ring_size)
+                       lo_water = 0;
+
+               hi_water = bp->rx_ring_size / 4;
+
+               if (hi_water <= lo_water)
+                       lo_water = 0;
+
+               hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
+               lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
+
+               if (hi_water > 0xf)
+                       hi_water = 0xf;
+               else if (hi_water == 0)
+                       lo_water = 0;
+               val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
+       }
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
+}
+
 static int
 bnx2_set_mac_link(struct bnx2 *bp)
 {
@@ -1044,13 +1092,16 @@ bnx2_set_mac_link(struct bnx2 *bp)
        /* Acknowledge the interrupt. */
        REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 
+       if (CHIP_NUM(bp) == CHIP_NUM_5709)
+               bnx2_init_rx_context0(bp);
+
        return 0;
 }
 
 static void
 bnx2_enable_bmsr1(struct bnx2 *bp)
 {
-       if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+       if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
            (CHIP_NUM(bp) == CHIP_NUM_5709))
                bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
                               MII_BNX2_BLK_ADDR_GP_STATUS);
@@ -1059,7 +1110,7 @@ bnx2_enable_bmsr1(struct bnx2 *bp)
 static void
 bnx2_disable_bmsr1(struct bnx2 *bp)
 {
-       if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+       if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
            (CHIP_NUM(bp) == CHIP_NUM_5709))
                bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
                               MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
@@ -1071,7 +1122,7 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp)
        u32 up1;
        int ret = 1;
 
-       if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
+       if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
                return 0;
 
        if (bp->autoneg & AUTONEG_SPEED)
@@ -1100,7 +1151,7 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp)
        u32 up1;
        int ret = 0;
 
-       if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
+       if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
                return 0;
 
        if (CHIP_NUM(bp) == CHIP_NUM_5709)
@@ -1125,7 +1176,7 @@ bnx2_enable_forced_2g5(struct bnx2 *bp)
 {
        u32 bmcr;
 
-       if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
+       if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
                return;
 
        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
@@ -1160,7 +1211,7 @@ bnx2_disable_forced_2g5(struct bnx2 *bp)
 {
        u32 bmcr;
 
-       if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
+       if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
                return;
 
        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
@@ -1210,7 +1261,7 @@ bnx2_set_link(struct bnx2 *bp)
                return 0;
        }
 
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                return 0;
 
        link_up = bp->link_up;
@@ -1220,16 +1271,22 @@ bnx2_set_link(struct bnx2 *bp)
        bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
        bnx2_disable_bmsr1(bp);
 
-       if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+       if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
            (CHIP_NUM(bp) == CHIP_NUM_5706)) {
-               u32 val;
+               u32 val, an_dbg;
 
-               if (bp->phy_flags & PHY_FORCED_DOWN_FLAG) {
+               if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
                        bnx2_5706s_force_link_dn(bp, 0);
-                       bp->phy_flags &= ~PHY_FORCED_DOWN_FLAG;
+                       bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
                }
                val = REG_RD(bp, BNX2_EMAC_STATUS);
-               if (val & BNX2_EMAC_STATUS_LINK)
+
+               bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
+               bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
+               bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
+
+               if ((val & BNX2_EMAC_STATUS_LINK) &&
+                   !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
                        bmsr |= BMSR_LSTATUS;
                else
                        bmsr &= ~BMSR_LSTATUS;
@@ -1238,7 +1295,7 @@ bnx2_set_link(struct bnx2 *bp)
        if (bmsr & BMSR_LSTATUS) {
                bp->link_up = 1;
 
-               if (bp->phy_flags & PHY_SERDES_FLAG) {
+               if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                        if (CHIP_NUM(bp) == CHIP_NUM_5706)
                                bnx2_5706s_linkup(bp);
                        else if (CHIP_NUM(bp) == CHIP_NUM_5708)
@@ -1252,18 +1309,18 @@ bnx2_set_link(struct bnx2 *bp)
                bnx2_resolve_flow_ctrl(bp);
        }
        else {
-               if ((bp->phy_flags & PHY_SERDES_FLAG) &&
+               if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
                    (bp->autoneg & AUTONEG_SPEED))
                        bnx2_disable_forced_2g5(bp);
 
-               if (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG) {
+               if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
                        u32 bmcr;
 
                        bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
                        bmcr |= BMCR_ANENABLE;
                        bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
 
-                       bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+                       bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
                }
                bp->link_up = 0;
        }
@@ -1309,7 +1366,7 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp)
        if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
                (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
 
-               if (bp->phy_flags & PHY_SERDES_FLAG) {
+               if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                        adv = ADVERTISE_1000XPAUSE;
                }
                else {
@@ -1317,7 +1374,7 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp)
                }
        }
        else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
-               if (bp->phy_flags & PHY_SERDES_FLAG) {
+               if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                        adv = ADVERTISE_1000XPSE_ASYM;
                }
                else {
@@ -1325,7 +1382,7 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp)
                }
        }
        else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
-               if (bp->phy_flags & PHY_SERDES_FLAG) {
+               if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                        adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
                }
                else {
@@ -1378,14 +1435,14 @@ bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
 
        if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
                speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
-       if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
+       if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
                speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
 
        if (port == PORT_TP)
                speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
                             BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
 
-       REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
+       bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
 
        spin_unlock_bh(&bp->phy_lock);
        bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
@@ -1400,7 +1457,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
        u32 adv, bmcr;
        u32 new_adv = 0;
 
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                return (bnx2_setup_remote_phy(bp, port));
 
        if (!(bp->autoneg & AUTONEG_SPEED)) {
@@ -1510,7 +1567,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
 }
 
 #define ETHTOOL_ALL_FIBRE_SPEED                                                \
-       (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ?                       \
+       (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
                (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
                (ADVERTISED_1000baseT_Full)
 
@@ -1530,9 +1587,9 @@ bnx2_set_default_remote_link(struct bnx2 *bp)
        u32 link;
 
        if (bp->phy_port == PORT_TP)
-               link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
+               link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
        else
-               link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
+               link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
 
        if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
                bp->req_line_speed = 0;
@@ -1574,17 +1631,19 @@ bnx2_set_default_remote_link(struct bnx2 *bp)
 static void
 bnx2_set_default_link(struct bnx2 *bp)
 {
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
-               return bnx2_set_default_remote_link(bp);
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
+               bnx2_set_default_remote_link(bp);
+               return;
+       }
 
        bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
        bp->req_line_speed = 0;
-       if (bp->phy_flags & PHY_SERDES_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                u32 reg;
 
                bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
 
-               reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
+               reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
                reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
                if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
                        bp->autoneg = 0;
@@ -1616,7 +1675,7 @@ bnx2_remote_phy_event(struct bnx2 *bp)
        u8 link_up = bp->link_up;
        u8 old_port;
 
-       msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
+       msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
 
        if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
                bnx2_send_heart_beat(bp);
@@ -1658,7 +1717,6 @@ bnx2_remote_phy_event(struct bnx2 *bp)
                                break;
                }
 
-               spin_lock(&bp->phy_lock);
                bp->flow_ctrl = 0;
                if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
                    (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
@@ -1680,7 +1738,6 @@ bnx2_remote_phy_event(struct bnx2 *bp)
                if (old_port != bp->phy_port)
                        bnx2_set_default_link(bp);
 
-               spin_unlock(&bp->phy_lock);
        }
        if (bp->link_up != link_up)
                bnx2_report_link(bp);
@@ -1693,7 +1750,7 @@ bnx2_set_remote_link(struct bnx2 *bp)
 {
        u32 evt_code;
 
-       evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
+       evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
        switch (evt_code) {
                case BNX2_FW_EVT_CODE_LINK_EVENT:
                        bnx2_remote_phy_event(bp);
@@ -1809,7 +1866,7 @@ bnx2_setup_phy(struct bnx2 *bp, u8 port)
        if (bp->loopback == MAC_LOOPBACK)
                return 0;
 
-       if (bp->phy_flags & PHY_SERDES_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                return (bnx2_setup_serdes_phy(bp, port));
        }
        else {
@@ -1844,7 +1901,7 @@ bnx2_init_5709s_phy(struct bnx2 *bp)
 
        bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
        bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
-       if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
+       if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
                val |= BCM5708S_UP1_2G5;
        else
                val &= ~BCM5708S_UP1_2G5;
@@ -1887,7 +1944,7 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
        val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
        bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
 
-       if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
                bnx2_read_phy(bp, BCM5708S_UP1, &val);
                val |= BCM5708S_UP1_2G5;
                bnx2_write_phy(bp, BCM5708S_UP1, val);
@@ -1905,14 +1962,13 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
                bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
        }
 
-       val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
+       val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
              BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
 
        if (val) {
                u32 is_backplane;
 
-               is_backplane = REG_RD_IND(bp, bp->shmem_base +
-                                         BNX2_SHARED_HW_CFG_CONFIG);
+               is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
                if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
                        bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
                                       BCM5708S_BLK_ADDR_TX_MISC);
@@ -1929,7 +1985,7 @@ bnx2_init_5706s_phy(struct bnx2 *bp)
 {
        bnx2_reset_phy(bp);
 
-       bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+       bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
 
        if (CHIP_NUM(bp) == CHIP_NUM_5706)
                REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
@@ -1968,7 +2024,7 @@ bnx2_init_copper_phy(struct bnx2 *bp)
 
        bnx2_reset_phy(bp);
 
-       if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
                bnx2_write_phy(bp, 0x18, 0x0c00);
                bnx2_write_phy(bp, 0x17, 0x000a);
                bnx2_write_phy(bp, 0x15, 0x310b);
@@ -1979,7 +2035,7 @@ bnx2_init_copper_phy(struct bnx2 *bp)
                bnx2_write_phy(bp, 0x18, 0x0400);
        }
 
-       if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
                bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
                               MII_BNX2_DSP_EXPAND_REG | 0x8);
                bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
@@ -2019,8 +2075,8 @@ bnx2_init_phy(struct bnx2 *bp)
        u32 val;
        int rc = 0;
 
-       bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
-       bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
+       bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
+       bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
 
        bp->mii_bmcr = MII_BMCR;
        bp->mii_bmsr = MII_BMSR;
@@ -2030,7 +2086,7 @@ bnx2_init_phy(struct bnx2 *bp)
 
         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
 
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                goto setup_phy;
 
        bnx2_read_phy(bp, MII_PHYSID1, &val);
@@ -2038,7 +2094,7 @@ bnx2_init_phy(struct bnx2 *bp)
        bnx2_read_phy(bp, MII_PHYSID2, &val);
        bp->phy_id |= val & 0xffff;
 
-       if (bp->phy_flags & PHY_SERDES_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                if (CHIP_NUM(bp) == CHIP_NUM_5706)
                        rc = bnx2_init_5706s_phy(bp);
                else if (CHIP_NUM(bp) == CHIP_NUM_5708)
@@ -2111,13 +2167,13 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
        bp->fw_wr_seq++;
        msg_data |= bp->fw_wr_seq;
 
-       REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
+       bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
 
        /* wait for an acknowledgement. */
        for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
                msleep(10);
 
-               val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
+               val = bnx2_shmem_rd(bp, BNX2_FW_MB);
 
                if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
                        break;
@@ -2134,7 +2190,7 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
                msg_data &= ~BNX2_DRV_MSG_CODE;
                msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
 
-               REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
+               bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
 
                return -EBUSY;
        }
@@ -2166,6 +2222,11 @@ bnx2_init_5709_context(struct bnx2 *bp)
        for (i = 0; i < bp->ctx_pages; i++) {
                int j;
 
+               if (bp->ctx_blk[i])
+                       memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
+               else
+                       return -ENOMEM;
+
                REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
                       (bp->ctx_blk_mapping[i] & 0xffffffff) |
                       BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
@@ -2226,7 +2287,7 @@ bnx2_init_context(struct bnx2 *bp)
 
                        /* Zero out the context. */
                        for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
-                               CTX_WR(bp, vcid_addr, offset, 0);
+                               bnx2_ctx_wr(bp, vcid_addr, offset, 0);
                }
        }
 }
@@ -2251,11 +2312,12 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp)
        good_mbuf_cnt = 0;
 
        /* Allocate a bunch of mbufs and save the good ones in an array. */
-       val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
+       val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
        while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
-               REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
+               bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
+                               BNX2_RBUF_COMMAND_ALLOC_REQ);
 
-               val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
+               val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
 
                val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
 
@@ -2265,7 +2327,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp)
                        good_mbuf_cnt++;
                }
 
-               val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
+               val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
        }
 
        /* Free the good ones back to the mbuf pool thus discarding
@@ -2276,7 +2338,7 @@ bnx2_alloc_bad_rbuf(struct bnx2 *bp)
                val = good_mbuf[good_mbuf_cnt];
                val = (val << 9) | val | 1;
 
-               REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
+               bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
        }
        kfree(good_mbuf);
        return 0;
@@ -2388,14 +2450,15 @@ bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
 static void
 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
 {
-       if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {
-               spin_lock(&bp->phy_lock);
+       spin_lock(&bp->phy_lock);
+
+       if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
                bnx2_set_link(bp);
-               spin_unlock(&bp->phy_lock);
-       }
        if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
                bnx2_set_remote_link(bp);
 
+       spin_unlock(&bp->phy_lock);
+
 }
 
 static inline u16
@@ -3014,7 +3077,7 @@ static int bnx2_poll(struct napi_struct *napi, int budget)
                rmb();
                if (likely(!bnx2_has_work(bnapi))) {
                        netif_rx_complete(bp->dev, napi);
-                       if (likely(bp->flags & USING_MSI_OR_MSIX_FLAG)) {
+                       if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
                                REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
                                       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
                                       bnapi->last_status_idx);
@@ -3051,10 +3114,10 @@ bnx2_set_rx_mode(struct net_device *dev)
                                  BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
        sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
 #ifdef BCM_VLAN
-       if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
+       if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
                rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
 #else
-       if (!(bp->flags & ASF_ENABLE_FLAG))
+       if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
                rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
 #endif
        if (dev->flags & IFF_PROMISC) {
@@ -3111,17 +3174,23 @@ bnx2_set_rx_mode(struct net_device *dev)
 }
 
 static void
-load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
+load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
        u32 rv2p_proc)
 {
        int i;
        u32 val;
 
+       if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
+               val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
+               val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
+               val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
+               rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
+       }
 
        for (i = 0; i < rv2p_code_len; i += 8) {
-               REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
+               REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
                rv2p_code++;
-               REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
+               REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
                rv2p_code++;
 
                if (rv2p_proc == RV2P_PROC1) {
@@ -3151,10 +3220,10 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
        int rc;
 
        /* Halt the CPU. */
-       val = REG_RD_IND(bp, cpu_reg->mode);
+       val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
        val |= cpu_reg->mode_value_halt;
-       REG_WR_IND(bp, cpu_reg->mode, val);
-       REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
+       bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
+       bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
 
        /* Load the Text area. */
        offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
@@ -3167,7 +3236,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
                        return rc;
 
                for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
-                       REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
+                       bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
                }
        }
 
@@ -3177,7 +3246,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
                int j;
 
                for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
-                       REG_WR_IND(bp, offset, fw->data[j]);
+                       bnx2_reg_wr_ind(bp, offset, fw->data[j]);
                }
        }
 
@@ -3187,7 +3256,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
                int j;
 
                for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
-                       REG_WR_IND(bp, offset, 0);
+                       bnx2_reg_wr_ind(bp, offset, 0);
                }
        }
 
@@ -3197,7 +3266,7 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
                int j;
 
                for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
-                       REG_WR_IND(bp, offset, 0);
+                       bnx2_reg_wr_ind(bp, offset, 0);
                }
        }
 
@@ -3208,19 +3277,19 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
                int j;
 
                for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
-                       REG_WR_IND(bp, offset, fw->rodata[j]);
+                       bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
                }
        }
 
        /* Clear the pre-fetch instruction. */
-       REG_WR_IND(bp, cpu_reg->inst, 0);
-       REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
+       bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
+       bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
 
        /* Start the CPU. */
-       val = REG_RD_IND(bp, cpu_reg->mode);
+       val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
        val &= ~cpu_reg->mode_value_halt;
-       REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
-       REG_WR_IND(bp, cpu_reg->mode, val);
+       bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
+       bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
 
        return 0;
 }
@@ -3492,7 +3561,7 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
                        wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
                }
 
-               if (!(bp->flags & NO_WOL_FLAG))
+               if (!(bp->flags & BNX2_FLAG_NO_WOL))
                        bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
 
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
@@ -3704,10 +3773,8 @@ bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
 
                val = REG_RD(bp, BNX2_NVM_COMMAND);
                if (val & BNX2_NVM_COMMAND_DONE) {
-                       val = REG_RD(bp, BNX2_NVM_READ);
-
-                       val = be32_to_cpu(val);
-                       memcpy(ret_val, &val, 4);
+                       __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
+                       memcpy(ret_val, &v, 4);
                        break;
                }
        }
@@ -3721,7 +3788,8 @@ bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
 static int
 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
 {
-       u32 cmd, val32;
+       u32 cmd;
+       __be32 val32;
        int j;
 
        /* Build the command word. */
@@ -3738,10 +3806,9 @@ bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
        REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
 
        memcpy(&val32, val, 4);
-       val32 = cpu_to_be32(val32);
 
        /* Write the data. */
-       REG_WR(bp, BNX2_NVM_WRITE, val32);
+       REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
 
        /* Address of the NVRAM to write to. */
        REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
@@ -3835,7 +3902,7 @@ bnx2_init_nvram(struct bnx2 *bp)
        }
 
 get_flash_size:
-       val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
+       val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
        val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
        if (val)
                bp->flash_size = val;
@@ -4140,18 +4207,18 @@ bnx2_init_remote_phy(struct bnx2 *bp)
 {
        u32 val;
 
-       bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
-       if (!(bp->phy_flags & PHY_SERDES_FLAG))
+       bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
+       if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
                return;
 
-       val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
+       val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
        if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
                return;
 
        if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
-               bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
+               bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
 
-               val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
+               val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
                if (val & BNX2_LINK_STATUS_SERDES_LINK)
                        bp->phy_port = PORT_FIBRE;
                else
@@ -4160,17 +4227,9 @@ bnx2_init_remote_phy(struct bnx2 *bp)
                if (netif_running(bp->dev)) {
                        u32 sig;
 
-                       if (val & BNX2_LINK_STATUS_LINK_UP) {
-                               bp->link_up = 1;
-                               netif_carrier_on(bp->dev);
-                       } else {
-                               bp->link_up = 0;
-                               netif_carrier_off(bp->dev);
-                       }
                        sig = BNX2_DRV_ACK_CAP_SIGNATURE |
                              BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
-                       REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
-                                  sig);
+                       bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
                }
        }
 }
@@ -4206,8 +4265,8 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
 
        /* Deposit a driver reset signature so the firmware knows that
         * this is a soft reset. */
-       REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
-                  BNX2_DRV_RESET_SIGNATURE_MAGIC);
+       bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
+                     BNX2_DRV_RESET_SIGNATURE_MAGIC);
 
        /* Do a dummy read to force the chip to complete all current transaction
         * before we issue a reset. */
@@ -4270,7 +4329,8 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
        spin_lock_bh(&bp->phy_lock);
        old_port = bp->phy_port;
        bnx2_init_remote_phy(bp);
-       if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port)
+       if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
+           old_port != bp->phy_port)
                bnx2_set_default_remote_link(bp);
        spin_unlock_bh(&bp->phy_lock);
 
@@ -4283,7 +4343,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
                rc = bnx2_alloc_bad_rbuf(bp);
        }
 
-       if (bp->flags & USING_MSIX_FLAG)
+       if (bp->flags & BNX2_FLAG_USING_MSIX)
                bnx2_setup_msix_tbl(bp);
 
        return rc;
@@ -4309,11 +4369,11 @@ bnx2_init_chip(struct bnx2 *bp)
 
        val |= (0x2 << 20) | (1 << 11);
 
-       if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
+       if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
                val |= (1 << 23);
 
        if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
-           (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
+           (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
                val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
 
        REG_WR(bp, BNX2_DMA_CONFIG, val);
@@ -4324,7 +4384,7 @@ bnx2_init_chip(struct bnx2 *bp)
                REG_WR(bp, BNX2_TDMA_CONFIG, val);
        }
 
-       if (bp->flags & PCIX_FLAG) {
+       if (bp->flags & BNX2_FLAG_PCIX) {
                u16 val16;
 
                pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
@@ -4438,25 +4498,28 @@ bnx2_init_chip(struct bnx2 *bp)
                      BNX2_HC_CONFIG_COLLECT_STATS;
        }
 
-       if (bp->flags & USING_MSIX_FLAG) {
+       if (bp->flags & BNX2_FLAG_USING_MSIX) {
+               u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
+                          BNX2_HC_SB_CONFIG_1;
+
                REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
                       BNX2_HC_MSIX_BIT_VECTOR_VAL);
 
-               REG_WR(bp, BNX2_HC_SB_CONFIG_1,
+               REG_WR(bp, base,
                        BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
                        BNX2_HC_SB_CONFIG_1_ONE_SHOT);
 
-               REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP_1,
+               REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
                        (bp->tx_quick_cons_trip_int << 16) |
                         bp->tx_quick_cons_trip);
 
-               REG_WR(bp, BNX2_HC_TX_TICKS_1,
+               REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
                        (bp->tx_ticks_int << 16) | bp->tx_ticks);
 
                val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
        }
 
-       if (bp->flags & ONE_SHOT_MSI_FLAG)
+       if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
                val |= BNX2_HC_CONFIG_ONE_SHOT;
 
        REG_WR(bp, BNX2_HC_CONFIG, val);
@@ -4510,6 +4573,7 @@ static void
 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
 {
        u32 val, offset0, offset1, offset2, offset3;
+       u32 cid_addr = GET_CID_ADDR(cid);
 
        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
                offset0 = BNX2_L2CTX_TYPE_XI;
@@ -4523,16 +4587,16 @@ bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
                offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
        }
        val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
-       CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
+       bnx2_ctx_wr(bp, cid_addr, offset0, val);
 
        val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
-       CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
+       bnx2_ctx_wr(bp, cid_addr, offset1, val);
 
        val = (u64) bp->tx_desc_mapping >> 32;
-       CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
+       bnx2_ctx_wr(bp, cid_addr, offset2, val);
 
        val = (u64) bp->tx_desc_mapping & 0xffffffff;
-       CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
+       bnx2_ctx_wr(bp, cid_addr, offset3, val);
 }
 
 static void
@@ -4543,7 +4607,7 @@ bnx2_init_tx_ring(struct bnx2 *bp)
        struct bnx2_napi *bnapi;
 
        bp->tx_vec = 0;
-       if (bp->flags & USING_MSIX_FLAG) {
+       if (bp->flags & BNX2_FLAG_USING_MSIX) {
                cid = TX_TSS_CID;
                bp->tx_vec = BNX2_TX_VEC;
                REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
@@ -4602,36 +4666,38 @@ bnx2_init_rx_ring(struct bnx2 *bp)
        bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
                             bp->rx_buf_use_size, bp->rx_max_ring);
 
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
+       bnx2_init_rx_context0(bp);
+
+       if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+               val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
+               REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
+       }
+
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
        if (bp->rx_pg_ring_size) {
                bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
                                     bp->rx_pg_desc_mapping,
                                     PAGE_SIZE, bp->rx_max_pg_ring);
                val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
                       BNX2_L2CTX_RBDC_JUMBO_KEY);
 
                val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
 
                val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
-               CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
+               bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
 
                if (CHIP_NUM(bp) == CHIP_NUM_5709)
                        REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
        }
 
-       val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
-       val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
-       val |= 0x02 << 8;
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
-
        val = (u64) bp->rx_desc_mapping[0] >> 32;
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
 
        val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
-       CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
+       bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
 
        ring_prod = prod = bnapi->rx_pg_prod;
        for (i = 0; i < bp->rx_pg_ring_size; i++) {
@@ -4693,7 +4759,7 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
        bp->rx_pg_ring_size = 0;
        bp->rx_max_pg_ring = 0;
        bp->rx_max_pg_ring_idx = 0;
-       if ((rx_space > PAGE_SIZE) && !(bp->flags & JUMBO_BROKEN_FLAG)) {
+       if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
                int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
 
                jumbo_size = size * pages;
@@ -4817,6 +4883,8 @@ bnx2_init_nic(struct bnx2 *bp)
        spin_lock_bh(&bp->phy_lock);
        bnx2_init_phy(bp);
        bnx2_set_link(bp);
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
+               bnx2_remote_phy_event(bp);
        spin_unlock_bh(&bp->phy_lock);
        return 0;
 }
@@ -4859,7 +4927,7 @@ bnx2_test_registers(struct bnx2 *bp)
                { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
 
                { 0x1000, 0, 0x00000000, 0x00000001 },
-               { 0x1004, 0, 0x00000000, 0x000f0001 },
+               { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
 
                { 0x1408, 0, 0x01c00800, 0x00000000 },
                { 0x149c, 0, 0x8000ffff, 0x00000000 },
@@ -5004,9 +5072,9 @@ bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
 
                for (offset = 0; offset < size; offset += 4) {
 
-                       REG_WR_IND(bp, start + offset, test_pattern[i]);
+                       bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
 
-                       if (REG_RD_IND(bp, start + offset) !=
+                       if (bnx2_reg_rd_ind(bp, start + offset) !=
                                test_pattern[i]) {
                                return -ENODEV;
                        }
@@ -5075,7 +5143,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
        struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
 
        tx_napi = bnapi;
-       if (bp->flags & USING_MSIX_FLAG)
+       if (bp->flags & BNX2_FLAG_USING_MSIX)
                tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
 
        if (loopback_mode == BNX2_MAC_LOOPBACK) {
@@ -5083,7 +5151,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
                bnx2_set_mac_loopback(bp);
        }
        else if (loopback_mode == BNX2_PHY_LOOPBACK) {
-               if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+               if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                        return 0;
 
                bp->loopback = PHY_LOOPBACK;
@@ -5216,7 +5284,7 @@ bnx2_test_loopback(struct bnx2 *bp)
 static int
 bnx2_test_nvram(struct bnx2 *bp)
 {
-       u32 buf[NVRAM_SIZE / 4];
+       __be32 buf[NVRAM_SIZE / 4];
        u8 *data = (u8 *) buf;
        int rc = 0;
        u32 magic, csum;
@@ -5253,7 +5321,7 @@ bnx2_test_link(struct bnx2 *bp)
 {
        u32 bmsr;
 
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
                if (bp->link_up)
                        return 0;
                return -ENODEV;
@@ -5301,11 +5369,15 @@ bnx2_test_intr(struct bnx2 *bp)
        return -ENODEV;
 }
 
+/* Determining link for parallel detection. */
 static int
 bnx2_5706_serdes_has_link(struct bnx2 *bp)
 {
        u32 mode_ctl, an_dbg, exp;
 
+       if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
+               return 0;
+
        bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
        bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
 
@@ -5316,7 +5388,7 @@ bnx2_5706_serdes_has_link(struct bnx2 *bp)
        bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
        bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
 
-       if (an_dbg & MISC_SHDW_AN_DBG_NOSYNC)
+       if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
                return 0;
 
        bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
@@ -5335,13 +5407,6 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
        int check_link = 1;
 
        spin_lock(&bp->phy_lock);
-       if (bp->phy_flags & PHY_FORCED_DOWN_FLAG) {
-               bnx2_5706s_force_link_dn(bp, 0);
-               bp->phy_flags &= ~PHY_FORCED_DOWN_FLAG;
-               spin_unlock(&bp->phy_lock);
-               return;
-       }
-
        if (bp->serdes_an_pending) {
                bp->serdes_an_pending--;
                check_link = 0;
@@ -5357,15 +5422,14 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
                                bmcr &= ~BMCR_ANENABLE;
                                bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
                                bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
-                               bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
+                               bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
                        }
                }
        }
        else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
-                (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
+                (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
                u32 phy2;
 
-               check_link = 0;
                bnx2_write_phy(bp, 0x17, 0x0f01);
                bnx2_read_phy(bp, 0x15, &phy2);
                if (phy2 & 0x20) {
@@ -5375,22 +5439,26 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
                        bmcr |= BMCR_ANENABLE;
                        bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
 
-                       bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
+                       bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
                }
        } else
                bp->current_interval = bp->timer_interval;
 
-       if (bp->link_up && (bp->autoneg & AUTONEG_SPEED) && check_link) {
+       if (check_link) {
                u32 val;
 
                bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
                bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
                bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
 
-               if (val & MISC_SHDW_AN_DBG_NOSYNC) {
-                       bnx2_5706s_force_link_dn(bp, 1);
-                       bp->phy_flags |= PHY_FORCED_DOWN_FLAG;
-               }
+               if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
+                       if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
+                               bnx2_5706s_force_link_dn(bp, 1);
+                               bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
+                       } else
+                               bnx2_set_link(bp);
+               } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
+                       bnx2_set_link(bp);
        }
        spin_unlock(&bp->phy_lock);
 }
@@ -5398,10 +5466,10 @@ bnx2_5706_serdes_timer(struct bnx2 *bp)
 static void
 bnx2_5708_serdes_timer(struct bnx2 *bp)
 {
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                return;
 
-       if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
+       if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
                bp->serdes_an_pending = 0;
                return;
        }
@@ -5441,14 +5509,15 @@ bnx2_timer(unsigned long data)
 
        bnx2_send_heart_beat(bp);
 
-       bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
+       bp->stats_blk->stat_FwRxDrop =
+               bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
 
        /* workaround occasional corrupted counters */
        if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
                REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
                                            BNX2_HC_COMMAND_STATS_NOW);
 
-       if (bp->phy_flags & PHY_SERDES_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                if (CHIP_NUM(bp) == CHIP_NUM_5706)
                        bnx2_5706_serdes_timer(bp);
                else
@@ -5467,7 +5536,7 @@ bnx2_request_irq(struct bnx2 *bp)
        struct bnx2_irq *irq;
        int rc = 0, i;
 
-       if (bp->flags & USING_MSI_OR_MSIX_FLAG)
+       if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
                flags = 0;
        else
                flags = IRQF_SHARED;
@@ -5496,12 +5565,12 @@ bnx2_free_irq(struct bnx2 *bp)
                        free_irq(irq->vector, dev);
                irq->requested = 0;
        }
-       if (bp->flags & USING_MSI_FLAG)
+       if (bp->flags & BNX2_FLAG_USING_MSI)
                pci_disable_msi(bp->pdev);
-       else if (bp->flags & USING_MSIX_FLAG)
+       else if (bp->flags & BNX2_FLAG_USING_MSIX)
                pci_disable_msix(bp->pdev);
 
-       bp->flags &= ~(USING_MSI_OR_MSIX_FLAG | ONE_SHOT_MSI_FLAG);
+       bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
 }
 
 static void
@@ -5533,7 +5602,7 @@ bnx2_enable_msix(struct bnx2 *bp)
        strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
 
        bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
-       bp->flags |= USING_MSIX_FLAG | ONE_SHOT_MSI_FLAG;
+       bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
        for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
                bp->irq_tbl[i].vector = msix_ent[i].vector;
 }
@@ -5546,15 +5615,15 @@ bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
        bp->irq_nvecs = 1;
        bp->irq_tbl[0].vector = bp->pdev->irq;
 
-       if ((bp->flags & MSIX_CAP_FLAG) && !dis_msi)
+       if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
                bnx2_enable_msix(bp);
 
-       if ((bp->flags & MSI_CAP_FLAG) && !dis_msi &&
-           !(bp->flags & USING_MSIX_FLAG)) {
+       if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
+           !(bp->flags & BNX2_FLAG_USING_MSIX)) {
                if (pci_enable_msi(bp->pdev) == 0) {
-                       bp->flags |= USING_MSI_FLAG;
+                       bp->flags |= BNX2_FLAG_USING_MSI;
                        if (CHIP_NUM(bp) == CHIP_NUM_5709) {
-                               bp->flags |= ONE_SHOT_MSI_FLAG;
+                               bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
                                bp->irq_tbl[0].handler = bnx2_msi_1shot;
                        } else
                                bp->irq_tbl[0].handler = bnx2_msi;
@@ -5606,7 +5675,7 @@ bnx2_open(struct net_device *dev)
 
        bnx2_enable_int(bp);
 
-       if (bp->flags & USING_MSI_FLAG) {
+       if (bp->flags & BNX2_FLAG_USING_MSI) {
                /* Test MSI to make sure it is working
                 * If MSI test fails, go back to INTx mode
                 */
@@ -5637,9 +5706,9 @@ bnx2_open(struct net_device *dev)
                        bnx2_enable_int(bp);
                }
        }
-       if (bp->flags & USING_MSI_FLAG)
+       if (bp->flags & BNX2_FLAG_USING_MSI)
                printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
-       else if (bp->flags & USING_MSIX_FLAG)
+       else if (bp->flags & BNX2_FLAG_USING_MSIX)
                printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
 
        netif_start_queue(dev);
@@ -5848,7 +5917,7 @@ bnx2_close(struct net_device *dev)
        bnx2_disable_int_sync(bp);
        bnx2_napi_disable(bp);
        del_timer_sync(&bp->timer);
-       if (bp->flags & NO_WOL_FLAG)
+       if (bp->flags & BNX2_FLAG_NO_WOL)
                reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
        else if (bp->wol)
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
@@ -5962,7 +6031,7 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        int support_serdes = 0, support_copper = 0;
 
        cmd->supported = SUPPORTED_Autoneg;
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
                support_serdes = 1;
                support_copper = 1;
        } else if (bp->phy_port == PORT_FIBRE)
@@ -5973,7 +6042,7 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        if (support_serdes) {
                cmd->supported |= SUPPORTED_1000baseT_Full |
                        SUPPORTED_FIBRE;
-               if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
+               if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
                        cmd->supported |= SUPPORTED_2500baseX_Full;
 
        }
@@ -6029,7 +6098,8 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
                goto err_out_unlock;
 
-       if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG))
+       if (cmd->port != bp->phy_port &&
+           !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
                goto err_out_unlock;
 
        if (cmd->autoneg == AUTONEG_ENABLE) {
@@ -6049,7 +6119,7 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                        advertising = cmd->advertising;
 
                } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
-                       if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ||
+                       if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
                            (cmd->port == PORT_TP))
                                goto err_out_unlock;
                } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
@@ -6072,7 +6142,7 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                                goto err_out_unlock;
 
                        if (cmd->speed == SPEED_2500 &&
-                           !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
+                           !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
                                goto err_out_unlock;
                }
                else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
@@ -6171,7 +6241,7 @@ bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
        struct bnx2 *bp = netdev_priv(dev);
 
-       if (bp->flags & NO_WOL_FLAG) {
+       if (bp->flags & BNX2_FLAG_NO_WOL) {
                wol->supported = 0;
                wol->wolopts = 0;
        }
@@ -6194,7 +6264,7 @@ bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
                return -EINVAL;
 
        if (wol->wolopts & WAKE_MAGIC) {
-               if (bp->flags & NO_WOL_FLAG)
+               if (bp->flags & BNX2_FLAG_NO_WOL)
                        return -EINVAL;
 
                bp->wol = 1;
@@ -6217,7 +6287,7 @@ bnx2_nway_reset(struct net_device *dev)
 
        spin_lock_bh(&bp->phy_lock);
 
-       if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
                int rc;
 
                rc = bnx2_setup_remote_phy(bp, bp->phy_port);
@@ -6226,7 +6296,7 @@ bnx2_nway_reset(struct net_device *dev)
        }
 
        /* Force a link down visible on the other side */
-       if (bp->phy_flags & PHY_SERDES_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
                spin_unlock_bh(&bp->phy_lock);
 
@@ -6838,7 +6908,7 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
        case SIOCGMIIREG: {
                u32 mii_regval;
 
-               if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+               if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                        return -EOPNOTSUPP;
 
                if (!netif_running(dev))
@@ -6857,7 +6927,7 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (!capable(CAP_NET_ADMIN))
                        return -EPERM;
 
-               if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
+               if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
                        return -EOPNOTSUPP;
 
                if (!netif_running(dev))
@@ -6929,7 +6999,7 @@ bnx2_get_5709_media(struct bnx2 *bp)
        if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
                return;
        else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
-               bp->phy_flags |= PHY_SERDES_FLAG;
+               bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
                return;
        }
 
@@ -6943,7 +7013,7 @@ bnx2_get_5709_media(struct bnx2 *bp)
                case 0x4:
                case 0x5:
                case 0x6:
-                       bp->phy_flags |= PHY_SERDES_FLAG;
+                       bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
                        return;
                }
        } else {
@@ -6951,7 +7021,7 @@ bnx2_get_5709_media(struct bnx2 *bp)
                case 0x1:
                case 0x2:
                case 0x4:
-                       bp->phy_flags |= PHY_SERDES_FLAG;
+                       bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
                        return;
                }
        }
@@ -6966,7 +7036,7 @@ bnx2_get_pci_speed(struct bnx2 *bp)
        if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
                u32 clkreg;
 
-               bp->flags |= PCIX_FLAG;
+               bp->flags |= BNX2_FLAG_PCIX;
 
                clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
 
@@ -7005,7 +7075,7 @@ bnx2_get_pci_speed(struct bnx2 *bp)
        }
 
        if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
-               bp->flags |= PCI_32BIT_FLAG;
+               bp->flags |= BNX2_FLAG_PCI_32BIT;
 
 }
 
@@ -7093,9 +7163,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                        rc = -EIO;
                        goto err_out_unmap;
                }
-               bp->flags |= PCIE_FLAG;
+               bp->flags |= BNX2_FLAG_PCIE;
                if (CHIP_REV(bp) == CHIP_REV_Ax)
-                       bp->flags |= JUMBO_BROKEN_FLAG;
+                       bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
        } else {
                bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
                if (bp->pcix_cap == 0) {
@@ -7108,12 +7178,12 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
 
        if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
                if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
-                       bp->flags |= MSIX_CAP_FLAG;
+                       bp->flags |= BNX2_FLAG_MSIX_CAP;
        }
 
        if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
                if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
-                       bp->flags |= MSI_CAP_FLAG;
+                       bp->flags |= BNX2_FLAG_MSI_CAP;
        }
 
        /* 5708 cannot support DMA addresses > 40-bit.  */
@@ -7136,7 +7206,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                goto err_out_unmap;
        }
 
-       if (!(bp->flags & PCIE_FLAG))
+       if (!(bp->flags & BNX2_FLAG_PCIE))
                bnx2_get_pci_speed(bp);
 
        /* 5706A0 may falsely detect SERR and PERR. */
@@ -7146,7 +7216,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                REG_WR(bp, PCI_COMMAND, reg);
        }
        else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
-               !(bp->flags & PCIX_FLAG)) {
+               !(bp->flags & BNX2_FLAG_PCIX)) {
 
                dev_err(&pdev->dev,
                        "5706 A1 can only be used in a PCIX bus, aborting.\n");
@@ -7155,20 +7225,20 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
 
        bnx2_init_nvram(bp);
 
-       reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
+       reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
 
        if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
            BNX2_SHM_HDR_SIGNATURE_SIG) {
                u32 off = PCI_FUNC(pdev->devfn) << 2;
 
-               bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
+               bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
        } else
                bp->shmem_base = HOST_VIEW_SHMEM_BASE;
 
        /* Get the permanent MAC address.  First we need to make sure the
         * firmware is actually running.
         */
-       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
+       reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
 
        if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
            BNX2_DEV_INFO_SIGNATURE_MAGIC) {
@@ -7177,7 +7247,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                goto err_out_unmap;
        }
 
-       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
+       reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
        for (i = 0, j = 0; i < 3; i++) {
                u8 num, k, skip0;
 
@@ -7191,42 +7261,41 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                if (i != 2)
                        bp->fw_version[j++] = '.';
        }
-       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);
+       reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
        if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
                bp->wol = 1;
 
        if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
-               bp->flags |= ASF_ENABLE_FLAG;
+               bp->flags |= BNX2_FLAG_ASF_ENABLE;
 
                for (i = 0; i < 30; i++) {
-                       reg = REG_RD_IND(bp, bp->shmem_base +
-                                            BNX2_BC_STATE_CONDITION);
+                       reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
                        if (reg & BNX2_CONDITION_MFW_RUN_MASK)
                                break;
                        msleep(10);
                }
        }
-       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);
+       reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
        reg &= BNX2_CONDITION_MFW_RUN_MASK;
        if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
            reg != BNX2_CONDITION_MFW_RUN_NONE) {
                int i;
-               u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR);
+               u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
 
                bp->fw_version[j++] = ' ';
                for (i = 0; i < 3; i++) {
-                       reg = REG_RD_IND(bp, addr + i * 4);
+                       reg = bnx2_reg_rd_ind(bp, addr + i * 4);
                        reg = swab32(reg);
                        memcpy(&bp->fw_version[j], &reg, 4);
                        j += 4;
                }
        }
 
-       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
+       reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
        bp->mac_addr[0] = (u8) (reg >> 8);
        bp->mac_addr[1] = (u8) reg;
 
-       reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
+       reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
        bp->mac_addr[2] = (u8) (reg >> 24);
        bp->mac_addr[3] = (u8) (reg >> 16);
        bp->mac_addr[4] = (u8) (reg >> 8);
@@ -7260,36 +7329,43 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
        if (CHIP_NUM(bp) == CHIP_NUM_5709)
                bnx2_get_5709_media(bp);
        else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
-               bp->phy_flags |= PHY_SERDES_FLAG;
+               bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
 
        bp->phy_port = PORT_TP;
-       if (bp->phy_flags & PHY_SERDES_FLAG) {
+       if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
                bp->phy_port = PORT_FIBRE;
-               reg = REG_RD_IND(bp, bp->shmem_base +
-                                    BNX2_SHARED_HW_CFG_CONFIG);
+               reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
                if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
-                       bp->flags |= NO_WOL_FLAG;
+                       bp->flags |= BNX2_FLAG_NO_WOL;
                        bp->wol = 0;
                }
-               if (CHIP_NUM(bp) != CHIP_NUM_5706) {
+               if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+                       /* Don't do parallel detect on this board because of
+                        * some board problems.  The link will not go down
+                        * if we do parallel detect.
+                        */
+                       if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
+                           pdev->subsystem_device == 0x310c)
+                               bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
+               } else {
                        bp->phy_addr = 2;
                        if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
-                               bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
+                               bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
                }
                bnx2_init_remote_phy(bp);
 
        } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
                   CHIP_NUM(bp) == CHIP_NUM_5708)
-               bp->phy_flags |= PHY_CRC_FIX_FLAG;
+               bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
        else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
                 (CHIP_REV(bp) == CHIP_REV_Ax ||
                  CHIP_REV(bp) == CHIP_REV_Bx))
-               bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG;
+               bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
 
        if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
            (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
            (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
-               bp->flags |= NO_WOL_FLAG;
+               bp->flags |= BNX2_FLAG_NO_WOL;
                bp->wol = 0;
        }
 
@@ -7363,13 +7439,13 @@ bnx2_bus_string(struct bnx2 *bp, char *str)
 {
        char *s = str;
 
-       if (bp->flags & PCIE_FLAG) {
+       if (bp->flags & BNX2_FLAG_PCIE) {
                s += sprintf(s, "PCI Express");
        } else {
                s += sprintf(s, "PCI");
-               if (bp->flags & PCIX_FLAG)
+               if (bp->flags & BNX2_FLAG_PCIX)
                        s += sprintf(s, "-X");
-               if (bp->flags & PCI_32BIT_FLAG)
+               if (bp->flags & BNX2_FLAG_PCI_32BIT)
                        s += sprintf(s, " 32-bit");
                else
                        s += sprintf(s, " 64-bit");
@@ -7519,7 +7595,7 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
        bnx2_netif_stop(bp);
        netif_device_detach(dev);
        del_timer_sync(&bp->timer);
-       if (bp->flags & NO_WOL_FLAG)
+       if (bp->flags & BNX2_FLAG_NO_WOL)
                reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
        else if (bp->wol)
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;