#define DRV_MODULE_NAME "bnx2"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "1.7.2"
-#define DRV_MODULE_RELDATE "January 21, 2008"
+#define DRV_MODULE_VERSION "1.7.5"
+#define DRV_MODULE_RELDATE "April 29, 2008"
#define RUN_AT(x) (jiffies + (x))
/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT (5*HZ)
-static const char version[] __devinitdata =
+static char version[] __devinitdata =
"Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
} board_t;
/* indexed by board_t, above */
-static const struct {
+static struct {
char *name;
} board_info[] __devinitdata = {
{ "Broadcom NetXtreme II BCM5706 1000Base-T" },
spin_unlock_bh(&bp->indirect_lock);
}
+static void
+bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
+{
+ bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
+}
+
+static u32
+bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
+{
+ return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
+}
+
static void
bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
{
else
fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
- REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
+ bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
}
static char *
return 0;
}
+static void
+bnx2_init_rx_context0(struct bnx2 *bp)
+{
+ u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
+
+ val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
+ val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
+ val |= 0x02 << 8;
+
+ if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+ u32 lo_water, hi_water;
+
+ if (bp->flow_ctrl & FLOW_CTRL_TX)
+ lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
+ else
+ lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
+ if (lo_water >= bp->rx_ring_size)
+ lo_water = 0;
+
+ hi_water = bp->rx_ring_size / 4;
+
+ if (hi_water <= lo_water)
+ lo_water = 0;
+
+ hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
+ lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
+
+ if (hi_water > 0xf)
+ hi_water = 0xf;
+ else if (hi_water == 0)
+ lo_water = 0;
+ val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
+ }
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
+}
+
static int
bnx2_set_mac_link(struct bnx2 *bp)
{
/* Acknowledge the interrupt. */
REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
+ if (CHIP_NUM(bp) == CHIP_NUM_5709)
+ bnx2_init_rx_context0(bp);
+
return 0;
}
if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
(CHIP_NUM(bp) == CHIP_NUM_5706)) {
- u32 val;
+ u32 val, an_dbg;
if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
bnx2_5706s_force_link_dn(bp, 0);
bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
}
val = REG_RD(bp, BNX2_EMAC_STATUS);
- if (val & BNX2_EMAC_STATUS_LINK)
+
+ bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
+ bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
+ bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
+
+ if ((val & BNX2_EMAC_STATUS_LINK) &&
+ !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
bmsr |= BMSR_LSTATUS;
else
bmsr &= ~BMSR_LSTATUS;
if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
- if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
+ if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
if (port == PORT_TP)
speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
- REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
+ bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
spin_unlock_bh(&bp->phy_lock);
bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
u32 link;
if (bp->phy_port == PORT_TP)
- link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
+ link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
else
- link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
+ link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
bp->req_line_speed = 0;
static void
bnx2_set_default_link(struct bnx2 *bp)
{
- if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
- return bnx2_set_default_remote_link(bp);
+ if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
+ bnx2_set_default_remote_link(bp);
+ return;
+ }
bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
bp->req_line_speed = 0;
bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
- reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
+ reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
bp->autoneg = 0;
u8 link_up = bp->link_up;
u8 old_port;
- msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
+ msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
bnx2_send_heart_beat(bp);
break;
}
- spin_lock(&bp->phy_lock);
bp->flow_ctrl = 0;
if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
(AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
if (old_port != bp->phy_port)
bnx2_set_default_link(bp);
- spin_unlock(&bp->phy_lock);
}
if (bp->link_up != link_up)
bnx2_report_link(bp);
{
u32 evt_code;
- evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
+ evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
switch (evt_code) {
case BNX2_FW_EVT_CODE_LINK_EVENT:
bnx2_remote_phy_event(bp);
bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
}
- val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
+ val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
if (val) {
u32 is_backplane;
- is_backplane = REG_RD_IND(bp, bp->shmem_base +
- BNX2_SHARED_HW_CFG_CONFIG);
+ is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
BCM5708S_BLK_ADDR_TX_MISC);
bp->fw_wr_seq++;
msg_data |= bp->fw_wr_seq;
- REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
+ bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
/* wait for an acknowledgement. */
for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
msleep(10);
- val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
+ val = bnx2_shmem_rd(bp, BNX2_FW_MB);
if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
break;
msg_data &= ~BNX2_DRV_MSG_CODE;
msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
- REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
+ bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
return -EBUSY;
}
for (i = 0; i < bp->ctx_pages; i++) {
int j;
+ if (bp->ctx_blk[i])
+ memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
+ else
+ return -ENOMEM;
+
REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
(bp->ctx_blk_mapping[i] & 0xffffffff) |
BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
/* Zero out the context. */
for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
- CTX_WR(bp, vcid_addr, offset, 0);
+ bnx2_ctx_wr(bp, vcid_addr, offset, 0);
}
}
}
good_mbuf_cnt = 0;
/* Allocate a bunch of mbufs and save the good ones in an array. */
- val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
+ val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
- REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
+ bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
+ BNX2_RBUF_COMMAND_ALLOC_REQ);
- val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
+ val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
good_mbuf_cnt++;
}
- val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
+ val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
}
/* Free the good ones back to the mbuf pool thus discarding
val = good_mbuf[good_mbuf_cnt];
val = (val << 9) | val | 1;
- REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
+ bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
}
kfree(good_mbuf);
return 0;
static void
bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
{
- if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {
- spin_lock(&bp->phy_lock);
+ spin_lock(&bp->phy_lock);
+
+ if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
bnx2_set_link(bp);
- spin_unlock(&bp->phy_lock);
- }
if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
bnx2_set_remote_link(bp);
+ spin_unlock(&bp->phy_lock);
+
}
static inline u16
int i;
u32 val;
+ if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
+ val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
+ val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
+ val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
+ rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
+ }
for (i = 0; i < rv2p_code_len; i += 8) {
REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
int rc;
/* Halt the CPU. */
- val = REG_RD_IND(bp, cpu_reg->mode);
+ val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
val |= cpu_reg->mode_value_halt;
- REG_WR_IND(bp, cpu_reg->mode, val);
- REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
+ bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
+ bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
/* Load the Text area. */
offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
return rc;
for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
- REG_WR_IND(bp, offset, le32_to_cpu(fw->text[j]));
+ bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
}
}
int j;
for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
- REG_WR_IND(bp, offset, fw->data[j]);
+ bnx2_reg_wr_ind(bp, offset, fw->data[j]);
}
}
int j;
for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
- REG_WR_IND(bp, offset, 0);
+ bnx2_reg_wr_ind(bp, offset, 0);
}
}
int j;
for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
- REG_WR_IND(bp, offset, 0);
+ bnx2_reg_wr_ind(bp, offset, 0);
}
}
int j;
for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
- REG_WR_IND(bp, offset, fw->rodata[j]);
+ bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
}
}
/* Clear the pre-fetch instruction. */
- REG_WR_IND(bp, cpu_reg->inst, 0);
- REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
+ bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
+ bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
/* Start the CPU. */
- val = REG_RD_IND(bp, cpu_reg->mode);
+ val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
val &= ~cpu_reg->mode_value_halt;
- REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
- REG_WR_IND(bp, cpu_reg->mode, val);
+ bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
+ bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
return 0;
}
}
get_flash_size:
- val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
+ val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
if (val)
bp->flash_size = val;
if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
return;
- val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
+ val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
return;
if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
- val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
+ val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
if (val & BNX2_LINK_STATUS_SERDES_LINK)
bp->phy_port = PORT_FIBRE;
else
if (netif_running(bp->dev)) {
u32 sig;
- if (val & BNX2_LINK_STATUS_LINK_UP) {
- bp->link_up = 1;
- netif_carrier_on(bp->dev);
- } else {
- bp->link_up = 0;
- netif_carrier_off(bp->dev);
- }
sig = BNX2_DRV_ACK_CAP_SIGNATURE |
BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
- REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
- sig);
+ bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
}
}
}
/* Deposit a driver reset signature so the firmware knows that
* this is a soft reset. */
- REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
- BNX2_DRV_RESET_SIGNATURE_MAGIC);
+ bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
+ BNX2_DRV_RESET_SIGNATURE_MAGIC);
/* Do a dummy read to force the chip to complete all current transaction
* before we issue a reset. */
bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
{
u32 val, offset0, offset1, offset2, offset3;
+ u32 cid_addr = GET_CID_ADDR(cid);
if (CHIP_NUM(bp) == CHIP_NUM_5709) {
offset0 = BNX2_L2CTX_TYPE_XI;
offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
}
val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
- CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
+ bnx2_ctx_wr(bp, cid_addr, offset0, val);
val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
- CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
+ bnx2_ctx_wr(bp, cid_addr, offset1, val);
val = (u64) bp->tx_desc_mapping >> 32;
- CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
+ bnx2_ctx_wr(bp, cid_addr, offset2, val);
val = (u64) bp->tx_desc_mapping & 0xffffffff;
- CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
+ bnx2_ctx_wr(bp, cid_addr, offset3, val);
}
static void
bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
bp->rx_buf_use_size, bp->rx_max_ring);
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
+ bnx2_init_rx_context0(bp);
+
+ if (CHIP_NUM(bp) == CHIP_NUM_5709) {
+ val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
+ REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
+ }
+
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
if (bp->rx_pg_ring_size) {
bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
bp->rx_pg_desc_mapping,
PAGE_SIZE, bp->rx_max_pg_ring);
val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
BNX2_L2CTX_RBDC_JUMBO_KEY);
val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
if (CHIP_NUM(bp) == CHIP_NUM_5709)
REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
}
- val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
- val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
- val |= 0x02 << 8;
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
-
val = (u64) bp->rx_desc_mapping[0] >> 32;
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
- CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
+ bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
ring_prod = prod = bnapi->rx_pg_prod;
for (i = 0; i < bp->rx_pg_ring_size; i++) {
spin_lock_bh(&bp->phy_lock);
bnx2_init_phy(bp);
bnx2_set_link(bp);
+ if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
+ bnx2_remote_phy_event(bp);
spin_unlock_bh(&bp->phy_lock);
return 0;
}
{ 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
{ 0x1000, 0, 0x00000000, 0x00000001 },
- { 0x1004, 0, 0x00000000, 0x000f0001 },
+ { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
{ 0x1408, 0, 0x01c00800, 0x00000000 },
{ 0x149c, 0, 0x8000ffff, 0x00000000 },
for (offset = 0; offset < size; offset += 4) {
- REG_WR_IND(bp, start + offset, test_pattern[i]);
+ bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
- if (REG_RD_IND(bp, start + offset) !=
+ if (bnx2_reg_rd_ind(bp, start + offset) !=
test_pattern[i]) {
return -ENODEV;
}
return -ENODEV;
}
+/* Determining link for parallel detection. */
static int
bnx2_5706_serdes_has_link(struct bnx2 *bp)
{
u32 mode_ctl, an_dbg, exp;
+ if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
+ return 0;
+
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
int check_link = 1;
spin_lock(&bp->phy_lock);
- if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
- bnx2_5706s_force_link_dn(bp, 0);
- bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
- spin_unlock(&bp->phy_lock);
- return;
- }
-
if (bp->serdes_an_pending) {
bp->serdes_an_pending--;
check_link = 0;
(bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
u32 phy2;
- check_link = 0;
bnx2_write_phy(bp, 0x17, 0x0f01);
bnx2_read_phy(bp, 0x15, &phy2);
if (phy2 & 0x20) {
} else
bp->current_interval = bp->timer_interval;
- if (bp->link_up && (bp->autoneg & AUTONEG_SPEED) && check_link) {
+ if (check_link) {
u32 val;
bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
- if (val & MISC_SHDW_AN_DBG_NOSYNC) {
- bnx2_5706s_force_link_dn(bp, 1);
- bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
- }
+ if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
+ if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
+ bnx2_5706s_force_link_dn(bp, 1);
+ bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
+ } else
+ bnx2_set_link(bp);
+ } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
+ bnx2_set_link(bp);
}
spin_unlock(&bp->phy_lock);
}
bnx2_send_heart_beat(bp);
- bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
+ bp->stats_blk->stat_FwRxDrop =
+ bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
/* workaround occasional corrupted counters */
if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
bnx2_init_nvram(bp);
- reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
+ reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
BNX2_SHM_HDR_SIGNATURE_SIG) {
u32 off = PCI_FUNC(pdev->devfn) << 2;
- bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
+ bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
} else
bp->shmem_base = HOST_VIEW_SHMEM_BASE;
/* Get the permanent MAC address. First we need to make sure the
* firmware is actually running.
*/
- reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
+ reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
BNX2_DEV_INFO_SIGNATURE_MAGIC) {
goto err_out_unmap;
}
- reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
+ reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
for (i = 0, j = 0; i < 3; i++) {
u8 num, k, skip0;
if (i != 2)
bp->fw_version[j++] = '.';
}
- reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);
+ reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
bp->wol = 1;
bp->flags |= BNX2_FLAG_ASF_ENABLE;
for (i = 0; i < 30; i++) {
- reg = REG_RD_IND(bp, bp->shmem_base +
- BNX2_BC_STATE_CONDITION);
+ reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
if (reg & BNX2_CONDITION_MFW_RUN_MASK)
break;
msleep(10);
}
}
- reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);
+ reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
reg &= BNX2_CONDITION_MFW_RUN_MASK;
if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
reg != BNX2_CONDITION_MFW_RUN_NONE) {
int i;
- u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR);
+ u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
bp->fw_version[j++] = ' ';
for (i = 0; i < 3; i++) {
- reg = REG_RD_IND(bp, addr + i * 4);
+ reg = bnx2_reg_rd_ind(bp, addr + i * 4);
reg = swab32(reg);
memcpy(&bp->fw_version[j], ®, 4);
j += 4;
}
}
- reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
+ reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
bp->mac_addr[0] = (u8) (reg >> 8);
bp->mac_addr[1] = (u8) reg;
- reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
+ reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
bp->mac_addr[2] = (u8) (reg >> 24);
bp->mac_addr[3] = (u8) (reg >> 16);
bp->mac_addr[4] = (u8) (reg >> 8);
bp->phy_port = PORT_TP;
if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
bp->phy_port = PORT_FIBRE;
- reg = REG_RD_IND(bp, bp->shmem_base +
- BNX2_SHARED_HW_CFG_CONFIG);
+ reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
bp->flags |= BNX2_FLAG_NO_WOL;
bp->wol = 0;
}
- if (CHIP_NUM(bp) != CHIP_NUM_5706) {
+ if (CHIP_NUM(bp) == CHIP_NUM_5706) {
+ /* Don't do parallel detect on this board because of
+ * some board problems. The link will not go down
+ * if we do parallel detect.
+ */
+ if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
+ pdev->subsystem_device == 0x310c)
+ bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
+ } else {
bp->phy_addr = 2;
if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
projects / linux-2.6-omap-h63xx.git / blobdiff