Merge branch 'ext3-latency-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-omap-h63xx.git] / drivers / net / bnx2x_reg.h

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 360a2564aa986918540b26f6d8824071408851ee..b8ce6fc927a06631d113df0e0da5cd328647c78c 100644 (file)
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -5410,7 +5410,7 @@
 #define PCICFG_COMMAND_INT_DISABLE             (1<<10)
 #define PCICFG_COMMAND_RESERVED                (0x1f<<11)
 #define PCICFG_STATUS_OFFSET                           0x06
-#define PCICFG_REVESION_ID                             0x08
+#define PCICFG_REVESION_ID_OFFSET                      0x08
 #define PCICFG_CACHE_LINE_SIZE                         0x0c
 #define PCICFG_LATENCY_TIMER                           0x0d
 #define PCICFG_BAR_1_LOW                               0x10
@@ -5438,7 +5438,7 @@
 #define PCICFG_PM_CSR_STATE                    (0x3<<0)
 #define PCICFG_PM_CSR_PME_ENABLE               (1<<8)
 #define PCICFG_PM_CSR_PME_STATUS               (1<<15)
-#define PCICFG_MSI_CAP_ID                              0x58
+#define PCICFG_MSI_CAP_ID_OFFSET                       0x58
 #define PCICFG_MSI_CONTROL_ENABLE              (0x1<<16)
 #define PCICFG_MSI_CONTROL_MCAP                (0x7<<17)
 #define PCICFG_MSI_CONTROL_MENA                (0x7<<20)
@@ -5446,7 +5446,7 @@
 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE  (0x1<<24)
 #define PCICFG_GRC_ADDRESS                             0x78
 #define PCICFG_GRC_DATA                                0x80
-#define PCICFG_MSIX_CAP_ID                             0xa0
+#define PCICFG_MSIX_CAP_ID_OFFSET                      0xa0
 #define PCICFG_MSIX_CONTROL_TABLE_SIZE         (0x7ff<<16)
 #define PCICFG_MSIX_CONTROL_RESERVED           (0x7<<27)
 #define PCICFG_MSIX_CONTROL_FUNC_MASK          (0x1<<30)
@@ -5843,6 +5843,7 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_ROM_VER2          0xca1a
 #define MDIO_PMA_REG_EDC_FFE_MAIN      0xca1b
 #define MDIO_PMA_REG_PLL_BANDWIDTH     0xca1d
+#define MDIO_PMA_REG_GEN_CTRL2         0xca1e
 #define MDIO_PMA_REG_MISC_CTRL0        0xca23
 #define MDIO_PMA_REG_LRM_MODE          0xca3f
 #define MDIO_PMA_REG_CDR_BANDWIDTH     0xca46