]> pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - drivers/net/dl2k.h
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild...
[linux-2.6-omap-h63xx.git] / drivers / net / dl2k.h
index e6623085e83487d590a79dabac02583dfd03ad49..266ec8777ca81797f0dfd92b22875229644e5584 100644 (file)
@@ -316,28 +316,6 @@ enum _mii_bmcr {
 };
 
 /* Basic Mode Status Register */
-typedef union t_MII_BMSR {
-       u16 image;
-       struct {
-               u16 ext_capability:1;   // bit 0
-               u16 japper_detect:1;    // bit 1
-               u16 link_status:1;      // bit 2
-               u16 an_ability:1;       // bit 3
-               u16 remote_fault:1;     // bit 4
-               u16 an_complete:1;      // bit 5
-               u16 preamble_supp:1;    // bit 6
-               u16 _bit_7:1;   // bit 7
-               u16 ext_status:1;       // bit 8
-               u16 media_100BT2_HD:1;  // bit 9
-               u16 media_100BT2_FD:1;  // bit 10
-               u16 media_10BT_HD:1;    // bit 11
-               u16 media_10BT_FD:1;    // bit 12
-               u16 media_100BX_HD:1;   // bit 13
-               u16 media_100BX_FD:1;   // bit 14
-               u16 media_100BT4:1;     // bit 15
-       } bits;
-} BMSR_t, *PBMSR_t;
-
 enum _mii_bmsr {
        MII_BMSR_100BT4 = 0x8000,
        MII_BMSR_100BX_FD = 0x4000,
@@ -386,18 +364,6 @@ enum _mii_anlpar {
 };
 
 /* Auto-Negotiation Expansion Register */
-typedef union t_MII_ANER {
-       u16 image;
-       struct {
-               u16 lp_negotiable:1;    // bit 0
-               u16 page_received:1;    // bit 1
-               u16 nextpagable:1;      // bit 2
-               u16 lp_nextpagable:1;   // bit 3
-               u16 pdetect_fault:1;    // bit 4
-               u16 _bit15_5:11;        // bit 15:5
-       } bits;
-} ANER_t, *PANER_t;
-
 enum _mii_aner {
        MII_ANER_PAR_DETECT_FAULT = 0x0010,
        MII_ANER_LP_NEXTPAGABLE = 0x0008,
@@ -407,19 +373,6 @@ enum _mii_aner {
 };
 
 /* MASTER-SLAVE Control Register */
-typedef union t_MII_MSCR {
-       u16 image;
-       struct {
-               u16 _bit_7_0:8; // bit 7:0
-               u16 media_1000BT_HD:1;  // bit 8
-               u16 media_1000BT_FD:1;  // bit 9
-               u16 port_type:1;        // bit 10
-               u16 cfg_value:1;        // bit 11
-               u16 cfg_enable:1;       // bit 12
-               u16 test_mode:3;        // bit 15:13
-       } bits;
-} MSCR_t, *PMSCR_t;
-
 enum _mii_mscr {
        MII_MSCR_TEST_MODE = 0xe000,
        MII_MSCR_CFG_ENABLE = 0x1000,
@@ -430,42 +383,17 @@ enum _mii_mscr {
 };
 
 /* MASTER-SLAVE Status Register */
-typedef union t_MII_MSSR {
-       u16 image;
-       struct {
-               u16 idle_err_count:8;   // bit 7:0
-               u16 _bit_9_8:2; // bit 9:8
-               u16 lp_1000BT_HD:1;     // bit 10
-               u16 lp_1000BT_FD:1;     // bit 11
-               u16 remote_rcv_status:1;        // bit 12
-               u16 local_rcv_status:1; // bit 13
-               u16 cfg_resolution:1;   // bit 14
-               u16 cfg_fault:1;        // bit 15
-       } bits;
-} MSSR_t, *PMSSR_t;
-
 enum _mii_mssr {
        MII_MSSR_CFG_FAULT = 0x8000,
        MII_MSSR_CFG_RES = 0x4000,
        MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
        MII_MSSR_REMOTE_RCVR = 0x1000,
-       MII_MSSR_LP_1000BT_HD = 0x0800,
-       MII_MSSR_LP_1000BT_FD = 0x0400,
+       MII_MSSR_LP_1000BT_FD = 0x0800,
+       MII_MSSR_LP_1000BT_HD = 0x0400,
        MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
 };
 
 /* IEEE Extened Status Register */
-typedef union t_MII_ESR {
-       u16 image;
-       struct {
-               u16 _bit_11_0:12;       // bit 11:0
-               u16 media_1000BT_HD:2;  // bit 12
-               u16 media_1000BT_FD:1;  // bit 13
-               u16 media_1000BX_HD:1;  // bit 14
-               u16 media_1000BX_FD:1;  // bit 15
-       } bits;
-} ESR_t, *PESR_t;
-
 enum _mii_esr {
        MII_ESR_1000BX_FD = 0x8000,
        MII_ESR_1000BX_HD = 0x4000,
@@ -473,6 +401,7 @@ enum _mii_esr {
        MII_ESR_1000BT_HD = 0x1000,
 };
 /* PHY Specific Control Register */
+#if 0
 typedef union t_MII_PHY_SCR {
        u16 image;
        struct {
@@ -490,6 +419,7 @@ typedef union t_MII_PHY_SCR {
                u16 xmit_fifo_depth:2;  // bit 15:14
        } bits;
 } PHY_SCR_t, *PPHY_SCR_t;
+#endif
 
 typedef enum t_MII_ADMIN_STATUS {
        adm_reset,