IVb. References
-http://www.smsc.com/main/datasheets/83c171.pdf
-http://www.smsc.com/main/datasheets/83c175.pdf
+http://www.smsc.com/main/tools/discontinued/83c171.pdf
+http://www.smsc.com/main/tools/discontinued/83c175.pdf
http://scyld.com/expert/NWay.html
http://www.national.com/pf/DP/DP83840A.html
0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 };
-/* The EPIC100 Rx and Tx buffer descriptors. */
+/*
+ * The EPIC100 Rx and Tx buffer descriptors. Note that these
+ * really ARE host-endian; it's not a misannotation. We tell
+ * the card to byteswap them internally on big-endian hosts -
+ * look for #ifdef CONFIG_BIG_ENDIAN in epic_open().
+ */
struct epic_tx_desc {
u32 txstatus;
int i, ret, option = 0, duplex = 0;
void *ring_space;
dma_addr_t ring_dma;
+ DECLARE_MAC_BUF(mac);
/* when built into the kernel, we only print version if device is found */
#ifndef MODULE
/* Note: the '175 does not have a serial EEPROM. */
for (i = 0; i < 3; i++)
- ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
+ ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(inw(ioaddr + LAN0 + i*4));
if (debug > 2) {
dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
if (ret < 0)
goto err_out_unmap_rx;
- printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
- dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq);
- for (i = 0; i < 5; i++)
- printk("%2.2x:", dev->dev_addr[i]);
- printk("%2.2x.\n", dev->dev_addr[i]);
+ printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %s\n",
+ dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq,
+ print_mac(mac, dev->dev_addr));
out:
return ret;
if (ep->chip_flags & MII_PWRDWN)
outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
-#if defined(__powerpc__) || defined(__sparc__) /* Big endian */
+ /* Tell the chip to byteswap descriptors on big-endian hosts */
+#ifdef CONFIG_BIG_ENDIAN
outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
inl(ioaddr + GENCTL);
outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
for (i = 0; i < 3; i++)
- outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
+ outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
ep->tx_threshold = TX_FIFO_THRESH;
outl(ep->tx_threshold, ioaddr + TxThresh);
for (i = 16; i > 0; i--)
outl(0x0008, ioaddr + TEST1);
-#if defined(__powerpc__) || defined(__sparc__) /* Big endian */
+#ifdef CONFIG_BIG_ENDIAN
outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
#else
outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
for (i = 0; i < 3; i++)
- outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
+ outl(le16_to_cpu(((__le16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
ep->tx_threshold = TX_FIFO_THRESH;
outl(ep->tx_threshold, ioaddr + TxThresh);
/* Initialize all Rx descriptors. */
for (i = 0; i < RX_RING_SIZE; i++) {
ep->rx_ring[i].rxstatus = 0;
- ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
+ ep->rx_ring[i].buflength = ep->rx_buf_sz;
ep->rx_ring[i].next = ep->rx_ring_dma +
(i+1)*sizeof(struct epic_rx_desc);
ep->rx_skbuff[i] = NULL;
skb_reserve(skb, 2); /* 16 byte align the IP header. */
ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
- ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
+ ep->rx_ring[i].rxstatus = DescOwn;
}
ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
skb->len, PCI_DMA_TODEVICE);
if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
- ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
+ ctrl_word = 0x100000; /* No interrupt */
} else if (free_count == TX_QUEUE_LEN/2) {
- ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
+ ctrl_word = 0x140000; /* Tx-done intr. */
} else if (free_count < TX_QUEUE_LEN - 1) {
- ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
+ ctrl_word = 0x100000; /* No Tx-done intr. */
} else {
/* Leave room for an additional entry. */
- ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
+ ctrl_word = 0x140000; /* Tx-done intr. */
ep->tx_full = 1;
}
- ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
+ ep->tx_ring[entry].buflength = ctrl_word | skb->len;
ep->tx_ring[entry].txstatus =
((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
- | cpu_to_le32(DescOwn);
+ | DescOwn;
ep->cur_tx++;
if (ep->tx_full)
for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
struct sk_buff *skb;
int entry = dirty_tx % TX_RING_SIZE;
- int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
+ int txstatus = ep->tx_ring[entry].txstatus;
if (txstatus & DescOwn)
break; /* It still hasn't been Txed */
rx_work_limit = budget;
/* If we own the next entry, it's a new packet. Send it up. */
- while ((ep->rx_ring[entry].rxstatus & cpu_to_le32(DescOwn)) == 0) {
- int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
+ while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) {
+ int status = ep->rx_ring[entry].rxstatus;
if (debug > 4)
printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
work_done++;
}
- ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
+ /* AV: shouldn't we add a barrier here? */
+ ep->rx_ring[entry].rxstatus = DescOwn;
}
return work_done;
}
epic_rx_err(dev, ep);
- if (netif_running(dev) && (work_done < budget)) {
+ if (work_done < budget) {
unsigned long flags;
int more;
projects / linux-2.6-omap-h63xx.git / blobdiff