Merge branch 'for-2.6.27' of git://git.marvell.com/mv643xx_eth into upstream-next

[linux-2.6-omap-h63xx.git] / drivers / net / ibm_emac / ibm_emac.h

diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
index 28c476f28c209840a2b8de9b54658bfbc9fd3e6f..97ed22bb4320c0e593fae8e02da5d06aabc1b653 100644 (file)
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ b/drivers/net/ibm_emac/ibm_emac.h
@@ -20,13 +20,13 @@
 #ifndef __IBM_EMAC_H_
 #define __IBM_EMAC_H_
 
-#include <linux/config.h>
 #include <linux/types.h>
 
 /* This is a simple check to prevent use of this driver on non-tested SoCs */
 #if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
     !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
-    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H)
+    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440GR)
 #error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
 #endif
 
@@ -109,6 +109,7 @@ struct emac_regs {
 #define EMAC_MR1_TFS_2K                        0x00080000
 #define EMAC_MR1_TR0_MULT              0x00008000
 #define EMAC_MR1_JPSM                  0x00000000
+#define EMAC_MR1_MWSW_001              0x00000000
 #define EMAC_MR1_BASE(opb)             (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
 #else
 #define EMAC_MR1_RFS_4K                        0x00180000
@@ -129,7 +130,7 @@ struct emac_regs {
                                         (freq) <= 83  ? EMAC_MR1_OBCI_83 : \
                                         (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
 #define EMAC_MR1_BASE(opb)             (EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
-                                        EMAC_MR1_MWSW_001 | EMAC_MR1_OBCI(opb))
+                                        EMAC_MR1_OBCI(opb))
 #endif
 
 /* EMACx_TMR0 */
@@ -246,6 +247,25 @@ struct emac_regs {
 #define EMAC_STACR_PCDA_SHIFT          5
 #define EMAC_STACR_PRA_MASK            0x1f
 
+/*
+ * For the 440SPe, AMCC inexplicably changed the polarity of
+ * the "operation complete" bit in the MII control register.
+ */
+#if defined(CONFIG_440SPE)
+static inline int emac_phy_done(u32 stacr)
+{
+       return !(stacr & EMAC_STACR_OC);
+};
+#define EMAC_STACR_START               EMAC_STACR_OC
+
+#else /* CONFIG_440SPE */
+static inline int emac_phy_done(u32 stacr)
+{
+       return stacr & EMAC_STACR_OC;
+};
+#define EMAC_STACR_START               0
+#endif /* !CONFIG_440SPE */
+
 /* EMACx_TRTR */
 #if !defined(CONFIG_IBM_EMAC4)
 #define EMAC_TRTR_SHIFT                        27