};
enum StirFifoCtlMask {
- FIFOCTL_EOF = 0x80,
- FIFOCTL_UNDER = 0x40,
- FIFOCTL_OVER = 0x20,
FIFOCTL_DIR = 0x10,
FIFOCTL_CLR = 0x08,
FIFOCTL_EMPTY = 0x04,
}
fcs = ~(crc32_le(~0, rx_buff->data, len));
- if (fcs != le32_to_cpu(get_unaligned((u32 *)(rx_buff->data+len)))) {
+ if (fcs != le32_to_cpu(get_unaligned((__le32 *)(rx_buff->data+len)))) {
pr_debug("crc error calc 0x%x len %d\n", fcs, len);
stir->stats.rx_errors++;
stir->stats.rx_crc_errors++;
{
int err;
unsigned long count, status;
+ unsigned long prev_count = 0x1fff;
/* Read FIFO status and count */
- for(;;) {
+ for (;; prev_count = count) {
err = read_reg(stir, REG_FIFOCTL, stir->fifo_status,
FIFO_REGS_SIZE);
if (unlikely(err != FIFO_REGS_SIZE)) {
if (space >= 0 && STIR_FIFO_SIZE - 4 > space + count)
return 0;
+ /* queue confused */
+ if (prev_count < count)
+ break;
+
/* estimate transfer time for remaining chars */
msleep((count * 8000) / stir->speed);
}
if(!net)
goto err_out1;
- SET_MODULE_OWNER(net);
SET_NETDEV_DEV(net, &intf->dev);
stir = netdev_priv(net);
stir->netdev = net;